JPS62221061A - Microcomputer - Google Patents

Abstract

PURPOSE:To easily control the stop state of a CPU and to simplify the constitution of a control circuit by stopping the clock of the CPU when an access is given to the peripheral device of low speed or a halt mode is attained for a stand-by function. CONSTITUTION:When a halt instruction is executed in the halt mode and in the stop mode of a CPU, the halt signal is outputted from an instruction decoder 22. Thus the output of a latch 50 is set at 1 in the next cycle, therefore CCK is set at 1 and the CPU is stopped. Then a halt mode is secured. When an interruption request signal INT is inputted during the halt mode, an RS flip-flop 58 is reset by the SCKB timing and the output of the flip-flop 58 is st at 0. Then the output of the latch 50 is set to 0 from the SCK timing of the next machine cycle. Thus the CCK, CCKB and CCKS are outputted in a normal way. As a result, the CPU is stopped even in a halt mode by stopping the result, the CPU is stopped even in a halt mode by stopping the clock of the CPU.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention relates to a central processing unit (hereinafter referred to as "CPU").
This invention relates to a microcomputer that performs stop control.

2. Description of the Related Art Generally, a microcomputer is composed of a CPU and peripheral devices. The CPU controls the peripheral device by writing data to and reading data from the peripheral device (hereinafter, such operations are referred to as "access").

In recent years, with advances in device technology, the operating speed of CPUs has become faster and faster. Therefore, when a CPU interfaces with a peripheral device made up of high-speed devices, the CPU can operate the peripheral device in synchronization with the operation of the CPU.

However, there are peripheral devices including low-speed devices that operate at a fixed speed, such as memory, and peripheral devices that have a configuration in which the timing that the CPU can access is limited (hereinafter referred to as "low-speed peripheral devices"). When the CPU accesses such a low-speed peripheral device, the CPU must continue accessing the low-speed peripheral device until the access to the low-speed peripheral device is completed, so that the operation of the CPU is synchronized with the operation of the low-speed peripheral device. In other words, the CPU is in a stopped state while accessing the peripheral device.

FIG. 2 shows a typical CP Ull and peripheral device 12 interface. An address is provided from the CP Ull to the peripheral device 12 via the address bus. Data corresponding to the address of peripheral device 12 is read onto the data bus by read signal PRD. Also, the light signal PWR
The data on the data bus output from c P Lll is written to the peripheral device 12 .

However, if the peripheral device 12 is a low-speed peripheral device as described above, a signal (hereinafter referred to as "R") requesting a stop is sent to the CPLI.
The interface is configured to output a DY signal (referred to as "DY signal") until the access is completed.

Conventionally, when the CPU accesses a low-speed peripheral device, C
In order to bring the PU into a halted state, a special wait cycle Mw in which the CPU does nothing is inserted into the CPU's operating machine cycle.

[Reference: UCOM-87 User's Manual (ITM-
6635) See page 43] FIG. 9 is a diagram showing insertion of the wait cycle Mw. CCK indicates the CPU clock.

When a low-speed peripheral device is accessed by machine cycle Mr, the low-speed peripheral device outputs a low level (hereinafter referred to as "0").
A valid RDY signal is input to the CPU. The CPU inserts a wait cycle MW between machine cycles M, . . . and the next machine cycle Mn+l to bring the CPU to a halt state. RDY signal is high level (hereinafter referred to as "1")
When this happens, the access is complete, and the CPU proceeds to the next machine cycle M n + +. As described above, conventionally, the stopped state of the CPLI has been achieved by controlling the machine cycle.

Furthermore, as microcomputers have rapidly become more highly integrated in recent years, increased power consumption has become a problem. Therefore, there is a tendency for CMOS devices with low power consumption to be adopted. Generally, a microcomputer using a CMOS device always has a standby mode that effectively utilizes the characteristics of CMO3. One of the standby modes is a mode in which the CPU stops the CPU's operating clock by executing an instruction to further reduce power consumption (hereinafter referred to as "HALT mode"). In HALT mode, the CPU's operating clock stops. , the CPU is in a stopped state.

FIG. 10 is a timing diagram showing the operation of the CPLI in HALT mode. When HALT mode is set by CPU instruction execution, HALT mode is set and CP
The U clock CCK remains at a high level (hereinafter referred to as "1") and stops. HAL due to occurrence of external interrupt, etc.
When the T mode is released, the CPU clock CCK starts operating again, so the CPU executes the next operation.

Problems to be Solved by the Invention As described above, there are two conditions that can be considered for the halt state of the CPU. Conventionally, stop control under these two conditions has been realized using different methods. That is, conventionally, it has been necessary to perform two systems of CPU stop control: machine cycle generation control capable of inserting wait cycles and clock control for HALT mode. Therefore, the CPU stop control becomes complicated and the circuit configuration becomes large, resulting in a major drawback in that the price of the microcomputer becomes high.

Therefore, an object of the present invention is to provide an inexpensive microcomputer that can easily control the CPU to stop by implementing control for two conditions that require the CPU to be stopped using the same control circuit.

Means for Solving the Problems The microcomputer of the present invention for solving the above problems includes a memory for storing programs or data;
A CPLI that executes a program, a peripheral device of the CPLI, and a ready signal generation that detects the start of a machine cycle in which the CPU accesses the peripheral device and generates a ready signal that synchronizes the operation of the CPU with the operation of the peripheral device. and a clock control device that detects a CPU stop signal or the ready signal generated when the CPLI executes a program and fixes the operating clock of the CPU to either a high or low level. ing.

Example Next, the present invention will be explained with reference to the drawings.

FIG. 2 is a diagram showing the ink face of the CPU II and peripheral device 12, as described above. An address is provided from the CPL III to the peripheral device 12 via the address bus. Data corresponding to the address of peripheral device 12 is read onto the data bus by read signal PRD.

Further, the data on the data bus output from CPLlll is written to the peripheral device 12 by the write signal PWR.

If the peripheral device 12 is a low-speed peripheral device, a stop request signal RDY is output to CPLll until the access is completed.

FIG. 2 is a block diagram of CP Ull. The output of the ROM21 in which the program is stored is the instruction decoder 2.
2 is done manually. When the instruction decoder 22 decodes the program, it outputs various control signals at respective timings. In addition, the output of the ROM 21 is output from the data bus 34.
is also output.

The RAM 23 where data is stored is the address bus 35.
Alternatively, an address is specified by the output SLA signal of the instruction decoder 22, and data on the data bus 34 is written by the output WR signal of the instruction decoder 22.

The contents of that address are read onto the data bus 34 by the RD double signal.

The output signals 5LTA, 5LTB of the instruction decoder 22 are sent to temporary registers TA26 and TA27 via anti-games 24 and 25, respectively. Then, the timing when the CPU clock CCKB is “1” (hereinafter referred to as “CCKB
(referred to as timing), each temporary register TA
26, the data on the data bus 34 is written to TA27. TA26 and TB27 are manpower for A side and B side of ALU28, respectively.

A timing diagram of the ALU 28 is shown in FIG. ALL
I28 is composed of a dynamic circuit in order to reduce the number of gates. This A L [28 is sampled at the timing when the CPU clock CCK is "1" (hereinafter referred to as "CCK timing"), and sends the operation specified by OP to the output of the instruction decoder 22 with the contents of TA26 and TB.
This is done between the contents of 27. Since ALU2B is a dynamic circuit, it is in a precharged state except at the CCK timing. The operation of ALL32B is as follows:
Since the timing is when CK is "1", the AOP signal is delayed by half a state to specify the operation. The output of A L U2B is sent to the temporary register TR29 when the clock CCKS is “
1” timing (referred to as “CCKS timing”). The output of TR29 is sent directly to the address bus 35.
At the same time, it is also output to the data bus 34.

The clock control circuit 30 is a circuit that creates a clock that operates the CPU peripheral devices. Instruction decoder output SL
Controlled by M signal and RDY signal, SCK, CCKS
Create clocks for CCKB and CCKS. The SLM signal and the RD multiplied signal are input to the AND gate 31, and its output PRD becomes a read signal for the peripheral device. The SLM signal and WR signal are input to the AND gate 32, and the output P
WR becomes a write signal to peripheral devices.

FIG. 3 is a circuit diagram of the clock control circuit 30.

The output of the oscillator 41 is frequency-divided by 2 with a dividing period 42 to become the system clock SCK, and is inverted by the inverter 43 to become the clock 5CKB. The SLM signal is sent to latch 44
Written when CK is at high level. The output of the latch 44 is written to the latch 45 when 5CKB is at high level. The output of latch 45 is input to AND gate 47 via inverter 46. Also, the SLM signal is an AND gate 47
．． 48 is also man-powered.

The RDY signal is passed through an inverter 56 to an AND gate 48.
is man-powered. The output of the AND gate 47.4B and the output of the RS flip-flop 58 are written to the latch 50 via the OR gate 49 at the timing when SCK is "1" (hereinafter referred to as "SCK timing").Latch 50
The output of is written to the latch 5I at the timing when 5CKB is 1 (hereinafter referred to as "5CKB timing"). latch 5
The output of 0 is manually supplied to an OR gate 53 and an inverter 57. When the output of latch 50 becomes “1”, CCK becomes “
'1', CCKB is fixed at '0'.The output of the latch 51 is input to the AND gate 54 via the inverter 55, so when the output of the latch 51 becomes '1', C
CKS is fixed at "0". But latch 50.5
When the content of 1 is “0”, CCK and CCKS are SC.
The clock is in phase with K.

Also, when the output HLT of the instruction decoder is “1”, 5C
The RS flip-flop 58 is set at KB timing. Further, the RS flip-flop 58 is reset when the interrupt acceptance signal INT from the interrupt processing device (not shown) is "1".

FIG. 7 shows a circuit for generating the RDY signal in a peripheral device. The PRD and PWR signals are input to a rise detector 72 via an OR gate 71. A signal obtained by inverting the level of SCK by an inverter 73 (therefore, the same signal as 5CKB) is input to the rising edge detector 72 as a clock. Therefore, when the peripheral device starts accessing, P
When WR and PRD change from "0" to "1", the rising edge detector 72 outputs a pulse of "1'" for one cycle of 5 CKB to reset the RS flip-flop 74.

Then, the output of the RS flip-flop 74 becomes "0"'. When the access of the peripheral device is completed, a set signal is outputted at a predetermined timing of the peripheral device.

This set signal is input to the AND gate 75 together with a signal obtained by inverting SCK by the inverter 73, and the output thereof is input to the RS flip-flop, so that the RS flip-flop 74 is set at the 5CKB timing.

Therefore, the RDY signal becomes "1".

Next, the operation of each part when the CPU accesses the peripheral device will be explained using the timing diagrams shown in FIGS. 4 and 6. An instruction to access a peripheral device is an instruction to add the contents of the A register in the RAM 23 and the contents of the PHDT register in the peripheral device specified by the address included in the instruction code, and write the result to the A register (hereinafter). “A.D.
DA.

Consider the PHDT instruction (referred to as ``'').ADD A.

The PHDT instruction consists of four machine cycles: M1, M2, M3, and M4.

In the M1 machine cycle, 5LASSLTA and RD times the signal are output. The A register in RAM 23 is specified by the SLA signal. Data is RAM23 from RD double signal
It is read from. The data read by the 5LTA signal is written to TA26.

In the M2 machine cycle, the 5LTB signal is output and P
The output of ROM21, which is the address that specifies the HDT, is T.
Written to B27. At the same time, TB27 is activated by AOP signal.
Since the contents of the PHDT are specified to pass through the ALU28, the PHDT is passed at the CCK timing of the M3 machine cycle.
The address is output to the address bus 35.

Next, in the M3 machine cycle, the PHDT register of the peripheral device 12 is accessed. Accessing the PHDT register requires six cycles from T1 to T6. M3
In the machine cycle, the PH is determined by the contents of the address bus 35.
DT is specified. In addition, SLM signal, PRD signal, 5
The LTB signal is output, and the AOP signal specifies addition.

Then, the clock control circuit 30 performs clock control as shown in FIG.

Since the SLM signal changes from "0" to "1", the output of the AND circuit 47 becomes "1" in the T1 cycle of the M3 state.
becomes. Then, the output of the latch 50 becomes “1”, so
CCK becomes "1" and CCKB becomes "0". Further, since the output of the latch 50 becomes 1 at the 5CKB timing of the T1 cycle, the output of the inverter 55 becomes "0". Therefore, 'CCCKS' becomes '0' after being output at the SCK timing of the T1 cycle.As a result, the address of the PHDT is latched in the TR29 and output to the address bus 35.

In the M3 machine cycle, the PRD signal changes from "0" to "1", so the RS flip-flop 74 is reset at the 5CKB timing, and the RDY signal becomes "0".

In the T2 cycle, the RDY signal is 0'', so latch 5
The output of 0.51 becomes “1”. Therefore, CCK is “1”
, CCKB becomes "0", and CCKS becomes "0". This state remains the same in subsequent T3 and T4 cycles.

The T5 cycle is one cycle before the T6 cycle when access to the PHDT register is completed.

In this T5 cycle, the set signal of the RS flip-flop 74 is output from the peripheral device, and the RDY signal becomes "1" at the 5CKB timing. Then, or gate 49
The output of is "0".

In the T6 cycle, the contents of the PHDT register are read from the peripheral device onto the data bus 34 by the PRD signal. In addition, since the output of the latch 50 becomes “0”, CCK and CC
KS, CCKB is SCK.

The operation is similar to SCK and 5CKB. As a result, T6
P on the data bus 34 at the CCKB timing of the cycle.
The contents of the HDT register are written to TB27.

In the M4 machine cycle, SLA and WR multiplied signals are output. The contents of TA26 and TB27 are added by ΔLU28 and the result is written to the A register in RAM 23 via TR29.

This completes the ADD A and PHDT commands, but M3
In the machine cycle, the CPU is stopped without executing anything from T1 to T5 cycles.

In other words, the stopped state of the CPU is realized by stopping the clock.

Furthermore, the CCKS clock is used as the write clock for the TR29. The reason is as follows. A
L [J28 is composed of a dynamic circuit and C
Sampled at CK timing.

Therefore, if it is stopped at "'1" like cycles T1 to T5 of the CCK, &M3 machine cycles, it will be in the sampling state during that time. When the sampling state becomes long, it becomes impossible to hold the output of the dynamic circuit,
The output of ALLI becomes undefined. , if TR29 is C
When writing is performed using CK and the human power of the TR becomes undefined, a so-called through current peculiar to CMOS devices flows due to the undefined human power, resulting in wasted power consumption. Therefore,
CCKS, which is not output while the CPU is stopped and CCK is "L", is used as the write signal for TR29.

Next, stopping the CPU in HALT mode will be explained using FIG. 8. When the HALT command is executed, the HLT signal is output from the command decoder 22. Then, in the next machine cycle, the output of latch 50 becomes “1”, so CC
K becomes "1", the CPU stops, and enters HALT mode. When the interrupt request signal INT is input manually during HALT mode, the RS flip-flop 58 is activated at the 5CKB timing.
is reset and the output becomes "0". Then, from the SCK timing of the next machine cycle, the output of the latch 50 becomes “
0'' and CCK, CCKB, and CCKS are output normally. Therefore, even in the HALT mode, by stopping the CPU clock, the CPLI is brought into a stopped state.

As described in detail, according to the present invention, when accessing a low-speed peripheral device or realizing the standby function HΔLT mode, the CPLI is stopped by the same method of stopping the CPU clock. can do. Therefore, the stop state control of the CPU is facilitated, and the control circuit configuration is simplified. As a result, this has the great effect of reducing the price of microcomputers.

[Brief explanation of drawings]

FIG. 1 is a detailed diagram of the CPU of the microcomputer according to the present invention, FIG. 2 is an interface diagram between the CPU and peripheral devices, FIG. 3 is a clock control circuit diagram of the present invention, and FIG. 4 is a diagram of the clock control circuit of the present invention. Timing diagram: Figure 5 is a timing diagram of ALU; Figure 6 is a timing diagram of ADD A and PHDT instructions; Figure 7 is a diagram of the RDY signal generation circuit of the present invention; Figure 8 is a diagram of HA
9 is a detailed timing diagram of the LT mode, FIG. 9 is an access timing diagram of a conventional peripheral device, and FIG. 10 is a conventional HALT mode timing diagram. (Main reference numbers) 11...CPLJ, 12...Peripheral device, 21...
ROM, 22...Instruction decoder, 23...RAM
. 24, 25.31.32.47.4B, 52.54.
75...And gate, 26, 27.29...Temporary register, 28...A
LU (arithmetic logic unit), 30...clock control circuit, 34...data bus, 35...address bus, 41...
Oscillator, 42... Frequency divider, 43, 46.55.56.57.73... Inverter, 44, 45.50.51... Latch, 49, 53.71... OR gate, 58, 74... RS Flip-flop, 72...rise detector

Claims (1)

[Claims] In a microcomputer consisting of a memory that stores programs and data, a central processing unit (CPU) that executes the programs, and peripheral devices of the CPU,
a ready signal that detects the start of a machine cycle in which the CPU writes data to the peripheral device or a machine cycle in which the CPU reads data from the peripheral device, and generates a ready signal to synchronize the operation of the CPU with the operation of the peripheral device; and a clock control device that detects the ready signal or a CPU stop signal generated by the CPU executing a program and fixes the operating clock of the CPU to either a high or low level. A microcomputer characterized by comprising: