JPS61165120A - Dynamic control system of clock pulse width - Google Patents

Abstract

PURPOSE:To make a clock generator and a synchronizing circuit unnecessary in each device, and to execute a control concisely by varying dynamically a clock pulse width by a clock controller so as to match with an object of an access. CONSTITUTION:In case of driving a memory 30, a control is executed so that a clock phi1 has the same pulse width as T0 for the most part, and phi2 becomes T1+T2, but a microprocessor 20 controls dynamically a clock width so that phi1 has the almost same pulse width as T0, with respect to a floppy disk device 40, but phi2 extends to the next machine cycle (T0, T1 and T2) from T1 of the first machine cycle, and phi1+phi2 become total 2 machine cycles. Also, a control is executed so that such a clock as can secure the time of read and write of a data in each adaptor is supplied to the microprocessor 20 from a clock controller 70, and the control is executed by a clock matching with each machine cycle of the microprocessor 20.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention relates to a clock synchronization method for data transfer in an information processing system that includes a microprocessor, a plurality of IO adapters, and a clock controller, and particularly relates to a clock synchronization method for data transfer in an information processing system that includes a microprocessor, a plurality of IO adapters, and a clock controller. When accessing different adapters.

The present invention relates to a clock width dynamic control method characterized in that a clock matching the adapter is generated by a clock controller 1 and supplied to a microprocessor.

With the development of integrated circuit technology, microprocessors (MP
U) Alternatively, not only memory but also memory control controllers, input/output control controllers, etc. have been integrated as one-chip LSIs and are now commercially available. And in the future.

Functional decentralization and parallel processing of systems are becoming more and more popular, and we are on the verge of offloading the work previously carried out by MPUs to other dedicated LSIs. By doing so, it is possible not only to reduce the amount of the entire system, but also to reduce the burden on the operating system (O3), and to achieve simplicity of control.

However, such dedicated LSIs, especially commercially available LSIs for input/output control, are designed to supply a low-speed basic clock through external terminals so that they can exclusively control input/output devices. .

On the other hand, a standard MPU operates with a high-speed clock of several Mllz, and generally one bus cycle takes T+~T□(
rn-3 to 5)) 2.For example, when executing an RI-IS message to the memory, an ALUS is output at the beginning of +' T +, and ALE (
The address is latched into an external launch circuit using the address load enable), and the address is used in several states after T2.

It is controlled asynchronously by putting data on the data bus. For example, when the MPU accesses to read data from a low-speed input/output device, MPLJ
Either stop its high-speed clock and wait until the input/output device is ready to output the data, or supply the MPU's internal high-speed clock to perform other work until the data is ready. An asynchronous method is adopted in which control is performed by interrupting the MPU at any point in time.

[Conventional technology] Traditionally, in such an asynchronous method of data transfer.

It has separate generators for generating high-speed clocks to supply to the CPU and generators for low-speed clocks to supply to input/output devices, and executes data transfer using a hunt-shake method. For example, when M PtJ reads data from an input/output device, when the MPU read command is given to the input/output control device, the input/output control device that receives that command will read the low-speed clock. This is used to perform input/output control for input/output devices. When data output is ready, an interrupt request signal is sent to the MPU, and if the MPU is ready to receive it, an acknowledge signal for the interrupt is returned, and the input/output control device loads the data onto the data bus. , and then processes it while synchronizing it with a high-speed clock.

[Problems to be solved by the invention]

Therefore, in this kind of asynchronous method of data transfer.

One clock generator is required for each device,
Furthermore, each device requires a special synchronization circuit to synchronize the data received from the outside with its own clock.
Not only does the amount of hardware increase, but also the control becomes complicated.

[Failure to solve the problem]

According to the present invention, in an information system comprising a microprocessor, an I-direct adapter, and a cross controller, when the microprocessor accesses an adapter with a different clock cycle, the clock pulse width is adjusted to match the object to be accessed. This is achieved by providing a dynamic control method for the clock pulse width, which is characterized in that the clock pulse width is dynamically varied by a clock controller to control the microprocessor.

[For production]

MPU basic clock φ1. The clock width of φ2 is
The memory accessed by the MPU, the object of the input/output control adapter, or a commercially available LSI is dynamically changed to reduce the speed and synchronize the clocks of each adapter with the operation of the MPU.

〔Example〕

Next, the dynamic control method of the clock pulse width according to the present invention will be explained with reference to the drawings.

FIG. 1 shows a microcomputer system in which a microprocessor (MPU) 20 and a memory 30 are connected in a common lot, and in addition, for example.

A floppy disk 40 is connected via an adapter 3.41, and in addition, adapters 1 and 51 for a printer device 50 are connected.
．． A diagram output control device 60 and a clock controller 70 are connected. In this case, for example, the adapter 3.41 for a floppy disk device has an MPU that controls seek operations, etc. in the 2 floppy disk device 40.
The data executed by commands from 20 and recorded in the floppy disk device 40 can be transferred to the MPU 20 itself via the common bus 10 or to the memory 30 using DMA (direct memory access), or vice versa.
The data from U20 or memory 30 is written to one disk drive 40. In this case, a commercially available LS'l called a floppy disk controller (FDC) is effectively used inside the floppy disk unit W40.

The amount of hardware in the floppy disk device 40 is reduced, and control is simplified.

However, since such a commercially available LS4 uses a low-speed basic clock different from the high-speed basic clock used in the MPU 20, it is necessary to match the clocks so that they are synchronized with each other. For example, if MPIJ is executing an operation to read data from the memory 30 without starting its FDC, as shown in FIG.
The DRAM controller outputs the row address (RAS) designation signal and the column address (CAS) designation signal of the memory between the TI and T2 clocks, taking a total of 3 r1ts as a machine cycle, and inputs the data to BA t7j. can. That is, when the MPU 20 reads and writes data to the memory 30.

MP [J2020, as shown in Figure 2 (al), To.

A logic circuit is formed to execute on a machine cycle basis consisting of TI and T2. Conversely, in such fixed machine cycles for the operation of devices other than memory, such as FDCs.

FDC data reading and writing cannot be guaranteed.

Therefore, as shown in FIG.
When a specific adapter within 0 is activated, control is performed so that φ2 can be dynamically changed so that it has a pulse width suitable for that adapter.

For example, when driving the memory 30, the fat
As shown in Fig. 2, the ψ1 clock has approximately the same pulse width as To, and the ψ2 clock is controlled so that TI+T2. As shown in , φ1 has almost the same pulse width as T, a, but φ2 has a pulse width from T1 of the first machine cycle to the next machine cycle (T o , TI, T
2), and the clock width is dynamically controlled so that φ1 → -φ2 is a total of 2 machine cycles, and the clock controller is used to lock the data to ensure the write time for each adapter. If it is controlled so as to be supplied to a microprocessor, it will be controlled with a clock that closely matches each machine cycle of the MPU.

In this case, each adapter has multiple registers, some of which are allocated to commercially available LSIs, and accessing these registers means that commercially available LSIs are activated. In that case, the basic clocks φ1 and φ2 stored in the microprocessor
MP the contents of that register to generate a pulse width of
After the startup command is issued from U, each adapter receives the clock from the clock controller 1-roller and transfers it to the MPU.

Use this as the basic clock.

In addition, when accessing a register other than the register allocated to a commercially available LSI, the contents of that register are transferred to the MPU.
20, the lMPU transfers φ1''-φ2 to To, TI,
The pulse width is generated to be equal to one machine cycle consisting of T2, and by inputting this, commercially available LS
I External Peripheral - 9 = Allow to control the circuit.

Next, when the microprocessor accesses each adapter, Figure 3 shows a circuit that increases the width of the φ2 pulse by one cycle among the clock pulses φ1 and φ2 given to the microprocessor from the clock controller. The case where data is transferred from the Fronbi disk device to the microprocessor via the FDC will be explained using the timing chart shown in FIG.

The circuit in Figure 3 is installed inside the clock controller,
5LFO9, Sl, which is activated to logic 1 when starting each adapter such as a channel interface, floppy disk, display or micro disk;
F O2, S'L, F O3゜5LFOC, 5LFOB
These signals are input to the OR circuit 201. For example, when accessing FDC, 5LFO'2 becomes logic 1.

The output of the OR circuit 201 also becomes logic 1. in this case.

As shown in Figure 4, the basic clock of the microprocessor (MPU) is the high-speed system clock CLO
O 25 T o is obtained by dividing S C by two.

0.25T1. 25,000T2. Wound 25T3 occurs 4 times in a row, totaling each T+ (i=o, 1°2) of the state.
It forms one of the Further, CL250 is generated simultaneously as the same clock as 025T3. Also, 5 above
LF02 signals are To and TI.

Among the three states of T2, TI is activated to logic I from the beginning. At this time, as shown in Figure 3, the second
In the state TI period, if RGSLO=1, the Nant gate 202 connected to the OR circuit 201
The output of is a logic O. And flip flop 20
The set input of 4 is connected to the output of the NAND gate 202 through the inverting circuit 203, and the reset input is directly connected to the output of the NAND gate 1202, so that during the T+ period, as shown in FIG. At the falling edge of the CL250 clock, the flip-flop 204 becomes set, and the CL2EX signal with one output becomes logic 1 from the T2 period, and the output *CL2EX signal becomes logic 0.
Since the EX signal is sent to logic I, this signal is T
2. The three consecutive stays of TO and TI become logic 1 and become 1.
It is reset on the falling edge of the CL 250 clock signal during the next second state T+ period. On the other hand, as shown in FIG. 3, CLK2T as the second clock φ2 is obtained by ANDing the CLK2B signal, which is the output of the AND gate 205 which inputs the *CL2EX signal, T2 signal, and *DMA signal, and the 025T2 clock signal. It is formed by the output signal CL K 2 T of the flip-flop 206 which is input to the gate 207 and whose output is input as a reset signal.

The CLK2T clock signal as this φ2 is.

The flip-flop 206 is 025T when the CLKIT clock signal ends at the falling edge of stage 1.
It is generated by being set at the falling edge of CLO3C clock and CLO3C clock.
Then, logic 1 becomes. and.

When the microprocessor executes an operation to access the FDC, s+pFo2=i, the flip-flop 204 is set to I in the next T2 stage 1, and the CL2EX signal is set to T2. While the logic is 1 in stay 1 of TO, T I, *CL2EX=0. C.L.
Since K2E=O, the flip-flop 206 always remains in the 7 so1 state.

The CL, K 2 T clock signal will continue to be a logic one.

As shown in FIG. 4, the CL2EX signal is set to logic 1 and the primary T2. From the 2nd state of TO to the end of the next T+ state, that is, the last C in the period of T1 state
When the CL2EX signal is reset at the falling edge of the L250 clock signal.

* Since CL2EX and CI-K2B are logic 1.

At the falling edge of the 025T2 and CLOS L clock signals of the next T2 state, the flip-flop 206 is reset and CLK2T becomes a logic zero. As a result of this, the first clock CL K I T as φ1
occurs only in the first To state.

After that, the second clock CL K 2 T as φ2 is TI, T2 . TO, T1. Only T2 has logic 1. In other words, the pulse width is extended by one cycle. For example, when the microprocessor 20 accesses the memory 30, as shown in the timing chart of FIG. 5, which is shown in more detail than FIG.
(φI) and CLK2T (φ2) is one cycle, that is, CLKIT is only To, and CLK
2T is controlled so that two cycles of T1 and T2 occur.

In this way, the present invention provides a basic clock φ1. from the clock controller to the microprocessor. By dynamically changing φ2 depending on the object to be accessed, it is possible to control commercially available I and Sl for adapters with different access times.

〔Effect of the invention〕

According to the present invention, when a microprocessor accesses different devices in a clock cycle, the clock controller supplies the microprocessor with a basic clock that matches the device at the time of access, so that each device has a clock. Since a generator and a synchronization circuit are not required, control is not only simplified, but also the lead amount of the entire system can be reduced by 14-1.

[Brief explanation of the drawing]

FIG. 1 is a configuration diagram of a microprocessor system. FIG. 2 shows the clock φ1. A diagram showing a φ2 signal. FIG. 3 is a circuit diagram of a main part of an embodiment of the invention. 4 and 5 are timing charts of the circuit diagram shown in FIG. 3. 10... Lotus. 20...Microprocessor. 30...Memory. 40...floppy disk. 50... Printer device. 41.51.60... I10 adapter. 70...Clock controller. 80...Kronk signal.

Claims (1)

[Claims] In an information system including a microprocessor, a plurality of IO adapters, and a clock controller, when the microprocessor accesses devices with different clock cycles, the clock controller operates a clock pulse width that matches the access target. A dynamic control method for the clock pulse width, which is characterized by controlling the microprocessor clock by varying the clock pulse width.