CN116881185A - JTAG interface signal switching method, system, equipment, device and medium - Google Patents

Abstract

The application discloses a JTAG interface signal switching method, a system, equipment, a device and a storage medium, wherein the method comprises the following steps: constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through JTAG interfaces; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface; responding to a first operation of a user, determining that the upper computer establishes signal connection with a first IP core through a four-wire signal interface; responding to a second operation of the user, determining that the upper computer establishes signal connection with a second IP core through a four-wire signal interface; and responding to a third operation of the user, determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface. The method can improve the efficiency of data transmission. The application can be widely applied to the technical field of chip driving.

Description

JTAG interface signal switching method, system, equipment, device and medium

Technical field

The present application relates to the field of chip driver technology, especially a JTAG interface signal switching method, system, equipment, device and storage medium.

Background technique

As the complexity of chips and the degree of core integration continue to increase, a large number of IP cores are used. Most IP cores provide a JTAG interface. In order to save chip pins, multiple IP cores need to share a JTAG interface. It is convenient to inherit and reuse the JTAG controller interface.

In the current technology, multiplexing multiple IP cores with one JTAG interface is usually through a multiplexing device, and the four-wire JTAG of multiple IP cores are connected to the multiplexed JTAG interface in the same line sequence. This will cause the following problems: when there is a problem with one or two PIN pins in the shared JTAG interface, all IP cores will be inaccessible. Therefore, there are still technical problems that need to be improved in related technologies.

Contents of the invention

The purpose of this application is to solve, at least to a certain extent, one of the technical problems existing in the prior art.

To this end, one purpose of the embodiments of the present application is to provide a JTAG interface signal switching method, system, device and storage medium, which method can improve the practicality of the JTAG interface and improve the efficiency of data transmission.

In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present application include: constructing a JTAG interface switching system; the JTAG interface switching system includes a host computer, a JTAG interface, a first IP core and a second IP core; the host computer The JTAG interface is connected to the first IP core and the second IP core; the JTAG interface includes a four-wire signal interface or a two-wire signal interface; in response to the user's first operation, it is determined that the host computer passes The four-wire signal interface establishes a signal connection with the first IP core; in response to the user's second operation, it is determined that the host computer establishes a signal connection with the second IP core through the four-wire signal interface; in response to The user's third operation is to determine that the host computer establishes a signal connection with the first IP core and/or the second IP core through the two-wire signal interface.

In addition, according to the method for switching JTAG interface signals in the above embodiments of the present invention, the following additional technical features may also be provided:

Further, in the embodiment of the present application, the step of establishing a signal connection with the first IP core through the four-wire signal interface in response to the user's first operation specifically includes: in response to the user placing the The register configuration is set to a first preset value, and a signal connection is established with the first IP core through the four-wire signal interface.

Further, in the embodiment of the present application, the step of determining that the host computer establishes a signal connection with the second IP core through the four-wire signal interface in response to the user's second operation specifically includes: responding to The user switches the register configuration from the first preset value to the second preset value on the user interface, and determines that the host computer establishes a signal connection with the second IP core through the four-wire signal interface.

Further, in the embodiment of the present application, in response to the user's third operation, it is determined that the host computer simultaneously establishes a signal connection with the first IP core and the second IP core through the two-wire signal interface. A step specifically includes: in response to the user switching the register configuration from the second preset value to the third preset value on the user interface, determining whether the host computer communicates with the host computer through the four-wire signal interface. The second IP core establishes the signal connection.

Further, in this embodiment of the present application, the switching method further includes: when the register of the user interface is configured as a fourth preset value, determining that the four-wire signal interface is faulty.

On the other hand, embodiments of the present application also provide a JTAG interface signal switching system, including: a construction unit for constructing a JTAG interface switching system; the JTAG interface switching system includes a host computer, a JTAG interface, a first IP core, and a third IP core. Two IP cores; the host computer is connected to the first IP core and the second IP core through the JTAG interface; the JTAG interface includes a four-wire signal interface or a two-wire signal interface; a first processing unit, In response to the user's first operation, it is determined that the host computer establishes a signal connection with the first IP core through the four-wire signal interface; a second processing unit is configured to respond to the user's second operation, determine that the The host computer establishes a signal connection with the second IP core through the four-wire signal interface; a third processing unit is configured to respond to the user's third operation and determine that the host computer communicates with the second IP core through the two-wire signal interface. The first IP core and/or the second IP core establishes a signal connection.

Furthermore, in this embodiment of the present application, the system further includes a fourth processing unit, which is configured to determine that a fault occurs in the four-wire signal interface when the register of the user interface is configured as a fourth preset value.

On the other hand, embodiments of the present application also provide an electronic device, including the JTAG interface signal switching system described in any one of the above aspects.

On the other hand, this application also provides a JTAG interface signal switching device, including:

at least one processor;

At least one memory for storing at least one program;

When the at least one program is executed by the at least one processor, the at least one processor implements a JTAG interface signal switching method as described in any one of the contents of the invention.

In addition, the present application also provides a storage medium in which processor-executable instructions are stored. When executed by the processor, the processor-executable instructions are used to execute a JTAG interface signal as described in any one of the above. Switch method.

The advantages and beneficial effects of the application will be set forth in part in the description below, and in part will be obvious from the description, or learned through practice of the application:

This application can realize the switching of the four-wire signal connection between the host computer and different IP cores according to the different operations of the user, or the establishment of two-wire signal connections between the host computer and two IP cores at the same time or separately, and can realize time-sharing multiplexing. At the same time as the four-wire signal connection, the signal connection between the host computer and the IP core can also be switched to a two-wire signal connection when the JTAG interface fails. This application can avoid the defect that when the four-wire signal interface of the JTAG interface fails, all IP cores cannot make signal connections with the host computer, and can improve the practicality of the JTAG interface and improve the efficiency of data transmission.

Description of the drawings

Figure 1 is a schematic diagram of the steps of a JTAG interface signal switching method in a specific embodiment of the present invention;

Figure 2 is a schematic structural diagram of a JTAG interface switching system in a specific embodiment of the present invention;

Figure 3 is an interface display diagram of the host computer when the four-wire signal interface of a JTAG interface fails in a specific embodiment of the present invention;

Figure 4 is an interface display diagram of a host computer when a JTAG interface is operating normally in a specific embodiment of the present invention;

Figure 5 is an interface display diagram of a host computer that enables the host computer to establish a signal connection with the IP core 1 through a four-wire signal interface in a specific embodiment of the present invention;

Figure 6 is an interface display diagram of a host computer that enables the host computer to establish a signal connection with the IP core 2 through a four-wire signal interface in a specific embodiment of the present invention;

Figure 7 is an interface display diagram of a host computer that allows the host computer to simultaneously establish signal connections with IP core 1 and IP core 2 through a two-wire signal interface in a specific embodiment of the present invention;

Figure 8 is a schematic structural diagram of a JTAG interface signal switching system in a specific embodiment of the present invention;

Figure 9 is a schematic structural diagram of a JTAG interface signal switching device in a specific embodiment of the present invention.

Detailed ways

The embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and the principles and processes of the JTAG interface signal switching method, system, device and storage medium in the embodiments of the present invention will be described below.

Referring to Figure 1, a JTAG interface signal switching method of the present invention may include the following steps:

S1. Construct a JTAG interface switching system; the JTAG interface switching system includes a host computer, a JTAG interface, a first IP core and a second IP core; the host computer communicates with the first IP core and the second IP core through the JTAG interface The second IP core is connected; the JTAG interface includes a four-wire signal interface or a two-wire signal interface.

In this step, this embodiment can design a JTAG interface switching system through simulation software or circuit design software. Users can also build a JTAG interface switching system. Specifically, referring to FIG. 2 , the JTAG interface switching system may include at least a host computer 1 , a JTAG interface 2 , a first IP core 3 and a second IP core 4 . The host computer 1 can be electrically connected to the JTAG interface 2 through lines, the first IP core 3 can be electrically connected to the JTAG interface 2 through lines, and the second IP core 4 can be electrically connected to the JTAG interface 2 through lines. Among them, the first IP core 3 and the second IP core 4 are connected to the JTAG interface 2 in parallel. Among them, the JTAG interface 2 may include a four-wire signal interface or a two-wire signal interface.

S2. In response to the user's first operation, determine that the host computer establishes a signal connection with the first IP core through the four-wire signal interface.

In this step, after completing the construction of the JTAG interface switching system, the host computer can burn the corresponding running or detection program. When the program is running, the user can modify the register configuration through the host computer interface so that the host computer can communicate with the host computer. Any IP core in the system implements a 4-wire signal connection.

S3. In response to the user's second operation, determine that the host computer establishes a signal connection with the second IP core through the four-wire signal interface.

In this step, when the program is running, the user can modify the register configuration through the interface of the host computer so that the host computer can achieve a 4-wire signal connection with another IP core in the system; the switched IP core is connected to the previous one. The IP cores to which the signals are connected are different.

S4. In response to the user's third operation, determine that the host computer establishes a signal connection with the first IP core and/or the second IP core through the two-wire signal interface.

In this step, when the program is running, the user can modify the register configuration through the interface of the host computer, so that the host computer can achieve a 2-wire signal connection with the two IP cores in the system at the same time; or the user can modify the register configuration through the interface of the host computer. Modify the register configuration to enable a 2-wire signal connection between the host computer and any IP core in the system.

Further, in some embodiments of the present application, in response to the user's first operation, the step of establishing a signal connection with the first IP core through the four-wire signal interface may specifically include: in response to the user's The interface sets the register configuration to a first preset value, and establishes a signal connection with the first IP core through the four-wire signal interface.

Further, in some embodiments of the present application, in response to the user's second operation, determining that the host computer establishes a signal connection with the second IP core through the four-wire signal interface specifically includes: responding After the user switches the register configuration from the first preset value to the second preset value in the user interface, it is determined that the host computer establishes a signal connection with the second IP core through the four-wire signal interface. .

Further, in some embodiments of the present application, in response to the user's third operation, it is determined that the host computer simultaneously establishes a connection with the first IP core and the second IP core through the two-wire signal interface. The step of signal connection specifically includes: in response to the user switching the register configuration from the second preset value to the third preset value in the user interface, determining that the host computer passes the four-wire signal interface Establish a signal connection with the second IP core.

Further, in some embodiments of the present application, the JTAG interface signal switching method also includes: when the register of the user interface is configured as a fourth preset value, determining that the four-wire signal interface is faulty.

The switching method in this embodiment will be described below with reference to Figures 4-7.

In this embodiment, the first preset value is "00001111", the second preset value is "00002222", the third preset value is "00002211", and the fourth preset value is "????????? ?”, the IP core of this application supports two-wire signal transmission and four-wire signal transmission modes.

First, set up the JTAG interface switching system; the JTAG interface switching system includes the host computer, JTAG interface, the first IP core and the second IP core; the host computer is connected to the first IP core and the second IP core through the JTAG interface; the JTAG interface has Four connecting lines, the JTAG interface includes a four-wire signal interface or a two-wire signal interface. In the four-wire interface mode, each line is TMS, TCK, TDI and TDO. In the two-wire interface mode, there can be two two-wire interfaces, two The line interfaces are TMS0 and TCK0, and TMS1 and TCK1 respectively.

Then run the preset program, and the system enters the four-wire interface communication mode, as shown in Figure 3. When the register configuration column on the host computer interface displays the fourth preset value as "??????????", Then it can be determined that the four-wire signal interface of the JTAG interface is faulty, and the running program needs to be stopped, and then the JTAG interface is further tested and the fault is eliminated through the existing equipment.

When there is no fault in the four-wire signal interface of the JTAG interface, the preset program runs normally. As shown in Figure 4-Figure 7, the register configuration column on the host computer interface displays "00000000". When the user changes "00000000" to "00001111", the host computer can establish a signal connection with the first IP core through the four-wire signal interface. When the user changes "00001111" to "00002222", the host computer establishes a signal connection with the second IP core through the four-wire signal interface. When the user changes "00002222" to "00002211", the host computer establishes a signal connection through the two-wire signal interface. At the same time, signal connections are established with the first IP core and the second IP core. When the user changes "00000000" to "00000011", the host computer can establish a signal connection with the first IP core through the two-wire signal interface. When the user changes "00000000" to "00000022", the host computer can establish a signal connection with the first IP core through the two-wire signal interface. The signal interface establishes a signal connection with the second IP core.

In addition, referring to Figure 8, corresponding to the method of Figure 1, embodiments of the present application also provide a JTAG interface signal switching system, which may include: a construction unit 101, a first processing unit 102, a second processing unit 103 and a third Three processing units 104. The construction unit 101 can be used to build a JTAG interface switching system; the JTAG interface switching system includes a host computer, a JTAG interface, a first IP core and a second IP core; the host computer communicates with the first IP core through the JTAG interface The core is connected to the second IP core; the JTAG interface includes a four-wire signal interface or a two-wire signal interface. The first processing unit 102 is configured to respond to the user's first operation and determine that the host computer establishes a signal connection with the first IP core through the four-wire signal interface. The second processing unit 103 is configured to respond to the user's second operation and determine that the host computer establishes a signal connection with the second IP core through the four-wire signal interface. The third processing unit 104 is configured to respond to the user's third operation and determine that the host computer establishes a signal connection with the first IP core and/or the second IP core through the two-wire signal interface.

Further, in some embodiments of the present application, the JTAG interface signal switching system may also include a fourth processing unit 105. The fourth processing unit 105 may be used to determine the four-wire The signal interface is faulty.

The contents in the above-mentioned JTAG interface signal switching method embodiment are applicable to this JTAG interface signal switching system embodiment. The specific functions implemented by this JTAG interface signal switching system embodiment are the same as the above-mentioned JTAG interface signal switching method embodiment. Moreover, the beneficial effects achieved are also the same as those achieved by the above-mentioned JTAG interface signal switching method embodiments.

Furthermore, embodiments of the present application also provide an electronic device, which may include at least one JTAG interface signal switching system described in any one of the above embodiments.

Corresponding to the method in Figure 1, embodiments of the present application also provide a JTAG interface signal switching device, the specific structure of which can be referred to Figure 9, including:

at least one processor;

At least one memory for storing at least one program;

When the at least one program is executed by the at least one processor, the at least one processor implements the JTAG interface signal switching method.

The contents of the above method embodiments are applicable to this device embodiment. The specific functions implemented by this device embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

Corresponding to the method in Figure 1, an embodiment of the present application also provides a storage medium in which processor-executable instructions are stored. When executed by the processor, the processor-executable instructions are used to execute the JTAG interface signal switching method.

The content in the above-mentioned JTAG interface signal switching method embodiment is applicable to this storage medium embodiment. The specific functions implemented by this storage medium embodiment are the same as the above-mentioned JTAG interface signal switching method embodiment, and the beneficial effects achieved are the same as The beneficial effects achieved by the above embodiments of the JTAG interface signal switching method are also the same.

In some alternative embodiments, the functions/operations noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending on the functionality/operations involved. Furthermore, the embodiments presented and described in the flowcharts of this application are provided by way of example for the purpose of providing a more comprehensive understanding of the technology. The disclosed methods are not limited to the operations and logical flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed and in which sub-operations described as part of a larger operation are performed independently.

Furthermore, although the present application is described in the context of functional modules, it should be understood that, unless stated to the contrary, one or more of the functions and/or features may be integrated in a single physical device and/or software module , or one or more functions and/or features may be implemented in separate physical devices or software modules. It will also be understood that a detailed discussion regarding the actual implementation of each module is not necessary for understanding the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be within the ordinary skill of an engineer, taking into account the properties, functions and internal relationships of the modules. Therefore, a person skilled in the art using ordinary skills will be able to implement the application as set forth in the claims without undue experimentation. It will also be understood that the specific concepts disclosed are illustrative only and are not intended to limit the scope of the application, which is to be determined by the full scope of the appended claims and their equivalents.

If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the existing technology or the part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including Several programs are used to cause a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), magnetic disk or optical disk, etc. that can store program code. medium.

The logic and/or steps represented in flowcharts or otherwise described herein, for example, may be considered a sequenced listing of an executable program for implementing the logical functions, which may be embodied in any computer-readable medium, For use with or in combination with program execution systems, devices or devices (such as computer-based systems, systems including processors or other systems that can retrieve programs from program execution systems, devices or devices and execute programs) or equipment. For the purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with a program execution system, apparatus, or device.

More specific examples (non-exhaustive list) of computer readable media include the following: electrical connections with one or more wires (electronic device), portable computer disk cartridges (magnetic device), random access memory (RAM), Read-only memory (ROM), erasable and programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium may even be paper or other suitable medium on which the program may be printed, as the paper or other medium may be optically scanned, for example, and subsequently edited, interpreted, or otherwise suitable as necessary. process to obtain the program electronically and then store it in computer memory.

It should be understood that various parts of the present application can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable program execution system. For example, if it is implemented in hardware, as in another embodiment, it can be implemented by any one or a combination of the following technologies known in the art: a logic gate circuit with a logic gate circuit for implementing a logic function on a data signal. Discrete logic circuits, application specific integrated circuits with suitable combinational logic gates, programmable gate arrays (PGA), field programmable gate arrays (FPGA), etc.

In the above description of this specification, reference to the description of the terms "one embodiment/example", "another embodiment/example" or "certain embodiments/examples" etc. is meant to be described in connection with the embodiment or example A specific feature, structure, material, or characteristic is included in at least one embodiment or example of this application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

Although the embodiments of the present application have been shown and described, those of ordinary skill in the art will understand that various changes, modifications, substitutions and modifications can be made to these embodiments without departing from the principles and purposes of the present application. The scope of the application is defined by the claims and their equivalents.

The above is a detailed description of the preferred implementation of the present application, but the present application is not limited to the embodiments. Those skilled in the art can also make various equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims (10)

1. A JTAG interface signal switching method is characterized by comprising the following steps:

constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface;

responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first IP core through the four-wire signal interface;

responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface;

and responding to a third operation of the user, determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface.

2. The method according to claim 1, wherein the step of establishing a signal connection with the first IP core through the four-wire signal interface in response to a first operation by a user, specifically comprises:

and in response to setting the register configuration to a first preset value in a user interface, establishing signal connection with the first IP core through the four-wire signal interface.

3. The method for switching signals of a JTAG interface according to claim 2, wherein said determining, in response to a second operation by a user, that said host establishes a signal connection with said second IP core through said four-wire signal interface comprises:

and responding to the fact that a user switches the register configuration from the first preset value to a second preset value in the user interface, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface.

4. The method for switching signals of a JTAG interface according to claim 3, wherein said determining, in response to a third operation by a user, that said host establishes signal connection with said first IP core and said second IP core simultaneously through said two-wire signal interface comprises:

and responding to the fact that a user switches the register configuration from the second preset value to a third preset value in the user interface, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface.

5. The JTAG interface signal switching method of claim 1, wherein said switching method further comprises: and when the register of the user interface is configured to be a fourth preset value, determining that the four-wire signal interface fails.

6. A JTAG interface signal switching system, comprising:

the building unit is used for building a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface;

the first processing unit is used for responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first IP core through the four-wire signal interface;

the second processing unit is used for responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface;

and the third processing unit is used for responding to a third operation of a user, and determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface.

7. The JTAG interface signal switching system of claim 6, further comprising a fourth processing unit for determining that the four-wire signal interface is malfunctioning when the registers of the user interface are configured to a fourth preset value.

8. An electronic device comprising the JTAG interface signal switching system of any of claims 6-7.

9. A JTAG interface signal switching apparatus, comprising:

at least one processor;

at least one memory for storing at least one program;

the at least one program, when executed by the at least one processor, causes the at least one processor to implement a JTAG interface signal switching method as claimed in any one of claims 1 to 5.

10. A computer readable storage medium having stored therein processor executable instructions which when executed by a processor are for performing a JTAG interface signal switching method as claimed in any of claims 1-5.