CN116881185A - JTAG interface signal switching method, system, equipment, device and medium - Google Patents
JTAG interface signal switching method, system, equipment, device and medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/102—Program control for peripheral devices where the programme performs an interfacing function, e.g. device driver
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0745—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in an input/output transactions management context
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0796—Safety measures, i.e. ensuring safe condition in the event of error, e.g. for controlling element
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/16—Error detection or correction of the data by redundancy in hardware
- G06F11/1608—Error detection by comparing the output signals of redundant hardware
- G06F11/1625—Error detection by comparing the output signals of redundant hardware in communications, e.g. transmission, interfaces
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Abstract
The application discloses a JTAG interface signal switching method, a system, equipment, a device and a storage medium, wherein the method comprises the following steps: constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through JTAG interfaces; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface; responding to a first operation of a user, determining that the upper computer establishes signal connection with a first IP core through a four-wire signal interface; responding to a second operation of the user, determining that the upper computer establishes signal connection with a second IP core through a four-wire signal interface; and responding to a third operation of the user, determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface. The method can improve the efficiency of data transmission. The application can be widely applied to the technical field of chip driving.
Description
Technical Field
The application relates to the technical field of chip driving, in particular to a JTAG interface signal switching method, a JTAG interface signal switching system, JTAG interface signal switching equipment, JTAG interface signal switching device and a JTAG interface signal storage medium.
Background
With the continuous improvement of the complexity core integration level of the chip, a large number of IP cores are used, most of the IP cores are provided with JTAG interfaces, and in order to save the pins of the chip, a plurality of IP cores need to commonly take one JTAG interface so as to conveniently inherit the JTAG controller interface for interconnection and multiplexing.
In the current technology, when multiple IP cores are multiplexed and connected by a JTAG interface, four-wire JTAG of multiple IP cores is connected to the multiplexed JTAG interface in the same wire sequence through a multiplexing device. This causes the following problems: when one or two PIN PINs in the common JTAG interface are problematic, all IP cores may be rendered inaccessible. Accordingly, there is still a technical problem in the related art that needs improvement.
Disclosure of Invention
The present application aims to solve at least one of the technical problems existing in the prior art to a certain extent.
Therefore, an object of the embodiments of the present application is to provide a method, a system, a device and a storage medium for switching signals of a JTAG interface, where the method can improve practicality of the JTAG interface and improve efficiency of data transmission.
In order to achieve the technical purpose, the technical scheme adopted by the embodiment of the application comprises the following steps: constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface; responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first IP core through the four-wire signal interface; responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface; and responding to a third operation of the user, determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface.
In addition, the method for switching the JTAG interface signals according to the embodiment of the present application may have the following additional technical features:
further, in an embodiment of the present application, the step of establishing a signal connection with the first IP core through the four-wire signal interface in response to a first operation of a user specifically includes: and in response to setting the register configuration to a first preset value in a user interface, establishing signal connection with the first IP core through the four-wire signal interface.
Further, in the embodiment of the present application, the step of determining, in response to a second operation of the user, that the upper computer establishes a signal connection with the second IP core through the four-wire signal interface specifically includes: and responding to the fact that a user switches the register configuration from the first preset value to a second preset value in the user interface, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface.
Further, in the embodiment of the present application, the step of determining, in response to a third operation of the user, that the upper computer establishes signal connection with the first I P core and the second I P core simultaneously through the two-wire signal interface specifically includes: and responding to the fact that a user switches the register configuration from the second preset value to a third preset value in the user interface, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface.
Further, in an embodiment of the present application, the switching method further includes: and when the register of the user interface is configured to be a fourth preset value, determining that the four-wire signal interface fails.
On the other hand, the embodiment of the application also provides a JTAG interface signal switching system, which comprises: the building unit is used for building a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first I P core and a second I P core; the upper computer is connected with the first I P core and the second I P core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface; the first processing unit is used for responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first I P core through the four-wire signal interface; the second processing unit is used for responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface; and the third processing unit is used for responding to a third operation of a user, and determining that the upper computer establishes signal connection with the first I P core and/or the second I P core through the two-wire signal interface.
Further, in an embodiment of the present application, the system further includes a fourth processing unit, where the fourth processing unit is configured to determine that the four-wire signal interface fails when the register of the user interface is configured to a fourth preset value.
On the other hand, the embodiment of the application also provides an electronic device, which comprises the JTAG interface signal switching system according to any one of the aspects.
On the other hand, the application also provides a JTAG interface signal switching device, which comprises:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement a JTAG interface signal switching method as in any of the inventive subject matter.
Furthermore, the present application provides a storage medium having stored therein processor executable instructions which when executed by a processor are adapted to perform a JTAG interface signal switching method as claimed in any one of the above.
The advantages and benefits of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
According to different operations of a user, the four-wire signal connection switching between the upper computer and different I P cores or the simultaneous or separate establishment of two-wire signal connection between the upper computer and two I P cores can be realized, the four-wire signal connection multiplexing can be realized, and meanwhile, the signal connection between the upper computer and I P cores can be switched into the two-wire signal connection when a JTAG interface fails. The application can avoid the defect that all I P cores cannot be connected with an upper computer when the four-wire signal interface of the JTAG interface fails, can improve the practicability of the JTAG interface and the efficiency of data transmission.
Drawings
FIG. 1 is a schematic diagram illustrating steps of a JTAG interface signal switching method according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a JTAG interface switching system according to an embodiment of the present application;
FIG. 3 is a diagram showing an interface of an upper computer when a four-wire signal interface of a JTAG interface fails according to an embodiment of the present application;
FIG. 4 is a diagram showing an interface of an upper computer when a JTAG interface is operating normally according to an embodiment of the present application;
FIG. 5 is a diagram showing an interface of an upper computer for enabling the upper computer to establish a signal connection with the I P core 1 through a four-wire signal interface according to an embodiment of the present application;
FIG. 6 is a diagram showing an interface of an upper computer for enabling the upper computer to establish a signal connection with the I P core 2 through a four-wire signal interface according to an embodiment of the present application;
FIG. 7 is a diagram showing an interface of an upper computer for enabling the upper computer to establish signal connection with the I P core 1 and the I P core 2 simultaneously through two-wire signal interfaces according to an embodiment of the present application;
FIG. 8 is a schematic diagram illustrating a JTAG interface signal switching system according to an embodiment of the present application;
fig. 9 is a schematic structural diagram of a JTAG interface signal switching apparatus according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below with reference to the accompanying drawings, to illustrate the principles and processes of the JTAG interface signal switching method, system, apparatus and storage medium in the embodiments of the present application.
Referring to fig. 1, a method for switching JTAG interface signals according to the present application may include the steps of:
s1, constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first I P core and a second I P core; the upper computer is connected with the first I P core and the second I P core through the JTAG interface; the JTAG interface includes a four-wire signal interface or a two-wire signal interface.
In this step, the present embodiment may design the JTAG interface switching system through simulation software or circuit design software. And a JTAG interface switching system can be built by a user. Specifically, referring to fig. 2, the JTAG interface switching system may include at least a host 1, a JTAG interface 2, a first I P core 3, and a second I P core 4. The upper computer 1 can be electrically connected with the JTAG interface 2 through a circuit, the first I P core 3 can be electrically connected with the JTAG interface 2 through a circuit, and the second I P core 4 can be electrically connected with the JTAG interface 2 through a circuit. Wherein the first I P core 3 is connected in parallel with the second I P core 4 to the JTAG interface 2. The JTAG interface 2 may include a four-wire signal interface or a two-wire signal interface, among others.
And S2, responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first I P core through the four-wire signal interface.
In this step, after the JTAG interface switching system is built, the upper computer may burn the corresponding operation or detection program, and when the program runs, the user may modify the register configuration through the interface of the upper computer, so that the upper computer and any one I P check in the system implement 4-wire signal connection.
And S3, responding to a second operation of the user, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface.
In the step, when the program runs, a user can modify the register configuration through the interface of the upper computer, so that the upper computer is connected with another I P check in the system by a 4-wire signal; wherein the I P core after the switch is different from the I P core that was previously signal connected.
And S4, responding to a third operation of a user, and determining that the upper computer establishes signal connection with the first I P core and/or the second I P core through the two-wire signal interface.
In the step, when the program runs, a user can modify the register configuration through an interface of the upper computer, so that the upper computer is connected with two I P cores in the system by 2-wire signals; or the configuration of the register can be modified through the interface of the upper computer, so that the upper computer can be connected with any I P core in the system by a 2-wire signal.
Further, in some embodiments of the present application, in response to a first operation by a user, the step of establishing a signal connection with the first I P core through the four-wire signal interface may specifically include: in response to a user setting a register configuration to a first preset value at a user interface, a signal connection is established with the first I P core through the four-wire signal interface.
Further, in some embodiments of the present application, in response to a second operation by the user, the step of determining that the upper computer establishes a signal connection with the second I P core through the four-wire signal interface specifically includes: and responding to the fact that a user switches the register configuration from the first preset value to a second preset value in the user interface, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface.
Further, in some embodiments of the present application, the step of determining, in response to a third operation by the user, that the upper computer establishes signal connection with the first I P core and the second I P core simultaneously through the two-wire signal interface specifically includes: and responding to the fact that a user switches the register configuration from the second preset value to a third preset value in the user interface, and determining that the upper computer establishes signal connection with the second I P core through the four-wire signal interface.
Further, in some embodiments of the present application, the JTAG interface signal switching method further includes: and when the register of the user interface is configured to be a fourth preset value, determining that the four-wire signal interface fails.
The switching method of the present embodiment is described below with reference to fig. 4 to 7.
In this embodiment, the first preset value is "00001111", the second preset value is "00002222", the third preset value is "00002211", and the fourth preset value is "", and the I P core of the present application supports two-wire signal transmission and four-wire signal transmission modes.
Firstly, constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first I P core and a second I P core; the upper computer is connected with the first I P core and the second I P core through JTAG interfaces; the JTAG interface has four connecting lines, and the JTAG interface includes four-wire signal interface or two-wire signal interface, and each line is TMS, TCK, TDI and TDO respectively when four-wire interface mode, can have two-wire interfaces when two-wire interface mode, and two-wire interface is TMS0 and TCK0 respectively to TMS1 and TCK1.
Then running a preset program, the system enters a four-wire interface communication mode, as shown in fig. 3, when a register configuration column on an interface of the upper computer displays a fourth preset value as 'the fourth preset value', the system can determine that a four-wire signal interface of the JTAG interface fails, and then the program needs to be stopped, then the JTAG interface is further detected, and the failure is eliminated through the existing equipment.
As shown in fig. 4 to 7, the register configuration column on the interface of the upper computer is displayed as "00000000". When the user changes "00000000" into "00001111", the host computer can establish signal connection with the first I P core through the four-wire signal interface. When the user changes '00001111' into '00002222', the upper computer establishes signal connection with the second I P core through the four-wire signal interface, and when the user changes '00002222' into '00002211', the upper computer establishes signal connection with the first I P core and the second I P core through the two-wire signal interface. When the user changes '00000000' into '00000011', the upper computer can be connected with the first I P core through the two-wire signal interface, and when the user changes '00000000' into '00000022', the upper computer can be connected with the second I P core through the two-wire signal interface.
In addition, referring to fig. 8, corresponding to the method of fig. 1, a JTAG interface signal switching system is further provided in an embodiment of the present application, which may include: a construction unit 101, a first processing unit 102, a second processing unit 103 and a third processing unit 104. The construction unit 101 may be configured to construct a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first I P core and a second I P core; the upper computer is connected with the first I P core and the second I P core through the JTAG interface; the JTAG interface includes a four-wire signal interface or a two-wire signal interface. The first processing unit 102 is configured to determine, in response to a first operation by a user, that the upper computer establishes a signal connection with the first I P core through the four-wire signal interface. And the second processing unit 103 is configured to determine that the upper computer establishes a signal connection with the second I P core through the four-wire signal interface in response to a second operation of the user. The third processing unit 104 is configured to determine, in response to a third operation by the user, that the upper computer establishes a signal connection with the first I P core and/or the second I P core through the two-wire signal interface.
Further, in some embodiments of the present application, the JTAG interface signal switching system may further include a fourth processing unit 105, and the fourth processing unit 105 may be configured to determine that the four-wire signal interface fails when the register of the user interface is configured to a fourth preset value.
The content in the above-mentioned JTAG interface signal switching method embodiment is suitable for the present JTAG interface signal switching system embodiment, the functions specifically realized by the present JTAG interface signal switching system embodiment are the same as those of the above-mentioned JTAG interface signal switching method embodiment, and the beneficial effects achieved are the same as those achieved by the above-mentioned JTAG interface signal switching method embodiment.
Further, an embodiment of the present application further provides an electronic device, which may include at least one JTAG interface signal switching system according to any one of the foregoing embodiments.
Corresponding to the method of fig. 1, the embodiment of the present application further provides a JTAG interface signal switching apparatus, with reference to fig. 9, including:
at least one processor;
at least one memory for storing at least one program;
and when the at least one program is executed by the at least one processor, the at least one processor is enabled to implement the JTAG interface signal switching method.
The content in the method embodiment is applicable to the embodiment of the device, and the functions specifically realized by the embodiment of the device are the same as those of the method embodiment, and the obtained beneficial effects are the same as those of the method embodiment.
Corresponding to the method of fig. 1, the embodiment of the present application further provides a storage medium having stored therein processor-executable instructions, which when executed by a processor are for performing the JTAG interface signal switching method.
The content in the above-mentioned JTAG interface signal switching method embodiment is applicable to the present storage medium embodiment, and the functions specifically implemented by the present storage medium embodiment are the same as those of the above-mentioned JTAG interface signal switching method embodiment, and the beneficial effects achieved by the above-mentioned JTAG interface signal switching method embodiment are the same as those achieved by the above-mentioned JTAG interface signal switching method embodiment.
In some alternative embodiments, the functions/acts noted in the block diagrams may occur out of the order noted in the operational illustrations. For example, two blocks shown in succession may in fact be executed substantially concurrently or the blocks may sometimes be executed in the reverse order, depending upon the functionality/acts involved. Furthermore, the embodiments presented and described in the flowcharts of the present application are provided by way of example in order to provide a more thorough understanding of the technology. The disclosed methods are not limited to the operations and logic flows presented herein. Alternative embodiments are contemplated in which the order of various operations is changed, and in which sub-operations described as part of a larger operation are performed independently.
Furthermore, while the application is described in the context of functional modules, it should be appreciated that, unless otherwise indicated, one or more of the functions and/or features may be integrated in a single physical device and/or software module or may be implemented in separate physical devices or software modules. It will also be appreciated that a detailed discussion of the actual implementation of each module is not necessary to an understanding of the present application. Rather, the actual implementation of the various functional modules in the apparatus disclosed herein will be apparent to those skilled in the art from consideration of their attributes, functions and internal relationships. Accordingly, one of ordinary skill in the art can implement the application as set forth in the claims without undue experimentation. It is also to be understood that the specific concepts disclosed are merely illustrative and are not intended to be limiting upon the scope of the application, which is to be defined in the appended claims and their full scope of equivalents.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art or in the form of a software product stored in a storage medium, including several programs for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
Logic and/or steps represented in the flowcharts or otherwise described herein, e.g., a ordered listing of executable programs for implementing logical functions, can be embodied in any computer-readable medium for use by or in connection with a program execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the programs from the program execution system, apparatus, or device and execute the programs. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the program execution system, apparatus, or device.
More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). In addition, the computer readable medium may even be paper or other suitable medium on which the program is printed, as the program may be electronically captured, via, for instance, optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner, if necessary, and then stored in a computer memory.
It is to be understood that portions of the present application may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented in hardware, as in another embodiment, may be implemented using any one or combination of the following techniques, as is well known in the art: discrete logic circuits having logic gates for implementing logic functions on data signals, application specific integrated circuits having suitable combinational logic gates, programmable Gate Arrays (PGAs), field Programmable Gate Arrays (FPGAs), and the like.
In the foregoing description of the present specification, reference has been made to the terms "one embodiment/example", "another embodiment/example", "certain embodiments/examples", and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
While embodiments of the present application have been shown and described, it will be understood by those of ordinary skill in the art that: many changes, modifications, substitutions and variations may be made to the embodiments without departing from the spirit and principles of the application, the scope of which is defined by the claims and their equivalents.
While the preferred embodiment of the present application has been described in detail, the present application is not limited to the embodiments described above, and various equivalent modifications and substitutions can be made by those skilled in the art without departing from the spirit of the present application, and these equivalent modifications and substitutions are intended to be included in the scope of the present application as defined in the appended claims.
Claims (10)
1. A JTAG interface signal switching method is characterized by comprising the following steps:
constructing a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface;
responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first IP core through the four-wire signal interface;
responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface;
and responding to a third operation of the user, determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface.
2. The method according to claim 1, wherein the step of establishing a signal connection with the first IP core through the four-wire signal interface in response to a first operation by a user, specifically comprises:
and in response to setting the register configuration to a first preset value in a user interface, establishing signal connection with the first IP core through the four-wire signal interface.
3. The method for switching signals of a JTAG interface according to claim 2, wherein said determining, in response to a second operation by a user, that said host establishes a signal connection with said second IP core through said four-wire signal interface comprises:
and responding to the fact that a user switches the register configuration from the first preset value to a second preset value in the user interface, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface.
4. The method for switching signals of a JTAG interface according to claim 3, wherein said determining, in response to a third operation by a user, that said host establishes signal connection with said first IP core and said second IP core simultaneously through said two-wire signal interface comprises:
and responding to the fact that a user switches the register configuration from the second preset value to a third preset value in the user interface, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface.
5. The JTAG interface signal switching method of claim 1, wherein said switching method further comprises: and when the register of the user interface is configured to be a fourth preset value, determining that the four-wire signal interface fails.
6. A JTAG interface signal switching system, comprising:
the building unit is used for building a JTAG interface switching system; the JTAG interface switching system comprises an upper computer, a JTAG interface, a first IP core and a second IP core; the upper computer is connected with the first IP core and the second IP core through the JTAG interface; the JTAG interface comprises a four-wire signal interface or a two-wire signal interface;
the first processing unit is used for responding to a first operation of a user, and determining that the upper computer establishes signal connection with the first IP core through the four-wire signal interface;
the second processing unit is used for responding to a second operation of a user, and determining that the upper computer establishes signal connection with the second IP core through the four-wire signal interface;
and the third processing unit is used for responding to a third operation of a user, and determining that the upper computer establishes signal connection with the first IP core and/or the second IP core through the two-wire signal interface.
7. The JTAG interface signal switching system of claim 6, further comprising a fourth processing unit for determining that the four-wire signal interface is malfunctioning when the registers of the user interface are configured to a fourth preset value.
8. An electronic device comprising the JTAG interface signal switching system of any of claims 6-7.
9. A JTAG interface signal switching apparatus, comprising:
at least one processor;
at least one memory for storing at least one program;
the at least one program, when executed by the at least one processor, causes the at least one processor to implement a JTAG interface signal switching method as claimed in any one of claims 1 to 5.
10. A computer readable storage medium having stored therein processor executable instructions which when executed by a processor are for performing a JTAG interface signal switching method as claimed in any of claims 1-5.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030163773A1 (en) * | 2002-02-26 | 2003-08-28 | O'brien James J. | Multi-core controller |
| US20060277436A1 (en) * | 2005-04-27 | 2006-12-07 | Mcgowan Robert A | Apparatus and method for coupling a plurality of test access ports to external test and debug facility |
| CN105182221A (en) * | 2015-10-09 | 2015-12-23 | 天津国芯科技有限公司 | JTAG multipath selector and connection method in SoC |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN107301144A (en) * | 2017-06-22 | 2017-10-27 | 湖南国科微电子股份有限公司 | A kind of jtag interface multiplexing method and device |
| US20210335435A1 (en) * | 2019-05-31 | 2021-10-28 | Micron Technology, Inc. | Jtag based architecture allowing multi-core operation |
| WO2022063255A1 (en) * | 2020-09-28 | 2022-03-31 | 上海商汤智能科技有限公司 | Chip system |
| CN114461479A (en) * | 2020-11-09 | 2022-05-10 | 哲库科技(上海)有限公司 | Method and device for debugging multimedia processing chip, storage medium and electronic equipment |
-
2023
- 2023-06-14 CN CN202310706362.1A patent/CN116881185A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030163773A1 (en) * | 2002-02-26 | 2003-08-28 | O'brien James J. | Multi-core controller |
| US20060277436A1 (en) * | 2005-04-27 | 2006-12-07 | Mcgowan Robert A | Apparatus and method for coupling a plurality of test access ports to external test and debug facility |
| CN105182221A (en) * | 2015-10-09 | 2015-12-23 | 天津国芯科技有限公司 | JTAG multipath selector and connection method in SoC |
| CN105550119A (en) * | 2016-01-29 | 2016-05-04 | 中国人民解放军国防科学技术大学 | Simulation device based on JTAG protocol |
| CN107301144A (en) * | 2017-06-22 | 2017-10-27 | 湖南国科微电子股份有限公司 | A kind of jtag interface multiplexing method and device |
| US20210335435A1 (en) * | 2019-05-31 | 2021-10-28 | Micron Technology, Inc. | Jtag based architecture allowing multi-core operation |
| WO2022063255A1 (en) * | 2020-09-28 | 2022-03-31 | 上海商汤智能科技有限公司 | Chip system |
| CN114461479A (en) * | 2020-11-09 | 2022-05-10 | 哲库科技(上海)有限公司 | Method and device for debugging multimedia processing chip, storage medium and electronic equipment |
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