CN114116582A

CN114116582A - Mainboard and electronic equipment

Info

Publication number: CN114116582A
Application number: CN202111346435.8A
Authority: CN
Inventors: 孙瑛琪; 柳胜杰; 李晶晶; 杨光林; 韩亚男
Original assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Current assignee: Chengdu Haiguang Integrated Circuit Design Co Ltd
Priority date: 2021-11-15
Filing date: 2021-11-15
Publication date: 2022-03-01

Abstract

The invention provides a mainboard and electronic equipment. The main board comprises a PCB board, a CPU chip and a DDR circuit which are interconnected are integrated on the PCB board, a DDR controller is arranged in the CPU chip, wherein the CPU chip is provided with a DDR interface for the external connection of the DDR controller; the signal end of the DDR circuit is directly connected with the DDR interface through a metal wire; and the DDR circuit is arranged on the front surface of the PCB, and a DDR signal test point is arranged on the back surface of the PCB relative to the position of the DDR circuit. The invention can test the signal quality of the DDR interface of the CPU chip.

Description

Mainboard and electronic equipment

Technical Field

The present invention relates to the field of electronic device motherboards, and in particular, to a motherboard and an electronic device.

Background

In the practical application of the motherboard, many problems related to DDR (Double Data Rate SDRAM) are found, but because there is no test point on the Memory bank of the existing motherboard, and the DDR granule is ball grid array package, the solder point is hidden under the DDR granule, so the DDR interface problem is tested and positioned, especially when the DDR interface signal Rate is not high, if the oscilloscope is used to observe the actual signal waveform, the oscilloscope probe cannot be close to the actual DDR granule pin position, and the real signal waveform quality at the DDR granule pin position cannot be observed, and further because the Memory bank is generally in the form of DIMM (Dual-Inline-Memory-Modules), and is connected with the CPU through the DIMM socket connector, the interference introduced by the DIMM socket connector cannot be eliminated when the oscilloscope is used to observe the signal waveform. In order to solve these problems, better observe the DDR signal quality, and find the root cause affecting the DDR signal rate and other problems, it is necessary to provide a new motherboard structure.

Disclosure of Invention

In order to solve the above problems, the present invention provides a motherboard and an electronic device, which are suitable for testing the signal quality of the DDR interface of the CPU chip.

In a first aspect, the present invention provides a motherboard, the motherboard includes a PCB board, the PCB board integrates a CPU chip and a DDR circuit, the CPU chip is embedded with a DDR controller, wherein,

the CPU chip is provided with a DDR interface for external connection of the DDR controller;

the signal end of the DDR circuit is directly connected with the DDR interface through a metal wire;

and the DDR circuit is arranged on the front surface of the PCB, and a DDR signal test point is arranged on the back surface of the PCB corresponding to the position of the DDR circuit.

Optionally, the DDR circuit employs RDIMM.

Optionally, the DDR circuit includes two sets of DDR particles, an RCD chip, and an SPD chip, wherein,

each group of DDR particles comprises a plurality of DDR particles, wherein a data signal of each DDR particle is directly connected to the DDR interface;

the RCD chip is used for dividing a group of command and address signals connected with the DDR interface into two groups of completely same command and address signals, the two groups of command and address signals are respectively connected with a group of DDR particles, and clock signals and chip selection signals are distributed to the two groups of DDR particles;

and the SPD chip is connected with the RCD chip through an SMBUS bus and is connected to an SMBUS interface of the CPU chip.

Optionally, the two groups of DDR grains include 18 DDR grains, where one group includes 10 DDR grains, 8 DDR grains are used for transmitting data signals, and 2 DDR grains are used for transmitting ECC signals; the other group includes 8 DDR grains for transmitting data signals.

Optionally, the 18 DDDR particles are designed by 2Rank and numbered sequentially from 0 to 17, all even-numbered DDR particles form a first Rank, and all odd-numbered DDR particles form a second Rank;

the first ranks are arranged in a column, the second ranks are arranged in a column, 1 DDR particle located in the middle of each column is used for transmitting 8-bit ECC signals, and 8 DDR particles on two sides are used for transmitting 64-bit data signals;

the two DDR particles used for transmitting the 8-bit ECC signal and the 8 DDR particles on one side of the DDR particles form a group of DDR particles together, and the 8 DDR particles on the other side of the DDR particles used for transmitting the 8-bit ECC signal form another group of DDR particles together.

Optionally, the 18 DDDR particles are arranged on the front surface of the PCB, and DDR signal test points are arranged on the back surface of the PCB opposite to the 18 DDR particles.

Optionally, the CPU chip is disposed on the front side of the PCB, a via hole is disposed beside a pin of the DDR interface, and a back side of the via hole is used as a DDR interface signal test point.

Optionally, the CPU chip is further provided with the following interfaces, including:

2 PCIe x16 interfaces for connecting 2 PCIe x16 slots;

4 SATA interfaces for connecting standard SATA disks;

a PCIe x2 interface for connecting one gigabit network chip I350;

2 USB interfaces.

Optionally, a BMC chip is integrated on the PCB, and the BMC chip is interconnected with the CPU chip through an SPI interface, an LPC interface, and a USB interface.

In a second aspect, the present invention provides an electronic device, which includes the above motherboard.

The mainboard and the electronic equipment provided by the invention are suitable for testing the signal quality of the DDR interface of the CPU chip, and because the DDR circuit is directly integrated on the mainboard and is not accessed through the connector, the influence introduced by the connector is eliminated, the maximum performance of the DDR interface of the CPU chip is conveniently tested, the signal quality can be better observed by using an oscilloscope, and the comparison research of the signal test and the performance test is realized. Simultaneously, the DDR circuit is integrated on the mainboard, the anti-vibration performance is stronger than that of the slot, and the system reliability is higher.

Drawings

FIG. 1 is a schematic structural diagram of a motherboard frame according to an embodiment of the present invention;

FIG. 2 is a schematic layout diagram of a motherboard PCB according to an embodiment of the invention;

fig. 3 is a schematic structural diagram of a motherboard frame according to an embodiment of the invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Some embodiments of the invention are described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.

Fig. 1 is a schematic diagram illustrating a frame structure of a motherboard according to an embodiment of the present invention. The main Board includes a PCB (Printed Circuit Board), hereinafter referred to as a PCB Board. As shown in fig. 1, a CPU chip and a DDR circuit which are interconnected are integrated on a PCB board, and a DDR controller is built in the CPU chip, wherein the CPU chip is provided with a DDR interface for external connection of the DDR controller; the signal end of the DDR circuit is directly connected with the DDR interface through a metal wire; and the DDR circuit is arranged on the front surface of the PCB, and a DDR signal test point is arranged on the back surface of the PCB relative to the position of the DDR circuit.

As an embodiment, the DDR circuit of this embodiment may adopt an RDIMM (Registered DIMM) mode. The RDIMM adds a register on a memory bank for transmission, and the register is positioned between the CPU and the DDR particles, so that the parallel transmission distance is reduced, and the parallel transmission effectiveness is ensured. Because of the high register efficiency, the capacity and frequency of the RDIMM is much easier to increase than unbuffered DIMMs.

Specifically, referring to fig. 1, the DDR circuit in the RDIMM mode includes two sets of DDR particles, 1 RCD chip, and 1 SPD chip. The RCD chip, namely a Registering Clock Driver, is used for caching command and address signals of the DDR controller, dividing the command and address signals from the DDR controller into two parts, and reducing the delay from the command and address signals to the DDR particles. The SPD chip, i.e. Serial Presence Detect, is an erasable memory in which many important information of the DDR circuit is recorded: one is a basic parameter such as frequency, capacity, timing, etc.; the other type is information such as the serial number of the memory module, the manufacturer code and the like. The SPD information is generally written into the SPD chip by the manufacturer according to the actual performance of the memory before the manufacturer leaves the factory.

The two groups of DDR particles include 18 DDR particles, which can be denoted as a group a and a group B, where the group a includes 10 DDR particles, 8 DDR particles are used to transmit data signals, and the other 2 DDR particles are used to transmit ECC (Error Correcting Code) signals. Group B includes 8 DDR particles for transmitting data signals. The data signals (including ECC signals) of each DDR particle are directly connected to the CPU DDR interface without any switching.

A group of command and address signals connected with a DDR interface of the CPU chip are divided into two groups A and B through the RCD chip. The group a command and address signal connections drive the group a 10 DDR grains. The group B command and address signal connections drive the group B8 DDR grains. A group of Command & Address signals transmitted by a CPU chip are divided into two groups of identical Command and Address signals by using an RCD chip, two groups of DDR particles positioned on two sides are respectively driven, signal wiring of a DIMM memory bank can be optimized, signal driving capacity is enhanced, and DDR interface speed is improved. The data rate of DDR4RDIMM memory bank can reach 3200MT/s at present. In addition, the RCD chip is also used for distributing a clock signal and a chip selection signal to the two groups of DDR particles. Referring to fig. 1, the chip select signal CS0 _ a and the clock signal CLK0 are connected to DDR8, DDR10, DDR12, DDR14, and DDR16, the chip select signal CSI _ a and the clock signal CLK1 are connected to DDR9, DDR11, DDR13, DDR15, and DDR17, the chip select signal CS0 _ B and the clock signal CLK2 are connected to DDR0, DDR2, DDR4, and DDR6, and the chip select signal CS1 _ B and the clock signal CLK3 are connected to DDR1, DDR3, DDR5, and DDR 7.

In addition, the SPD chip is connected to the RCD chip through an SMBUS (System Management Bus) and connected to an SMBUS interface of the CPU chip. By configuring the DDR particles, the DDR particles can be directly configured through a DDR interface of the CPU, configuration data can be written into an SPD chip, and the DDR particles are configured through the SPD chip.

Of course, DDR circuitry is not limited to RDIMM. For example, the mode may be an LRDIMM (Load Reduced DIMM). Compared to RDIMM, LRDIMM does not use complex registers, but simply buffers, which reduces the power load on the lower motherboard but has little impact on memory performance. In addition, the Register chip on the RDIMM Memory is changed into an imb (isolation Memory buffer) Memory isolation buffer chip by the LRDIMM Memory, which has the direct advantages of reducing the Memory bus load and further improving the Memory support capacity.

The mainboard provided by the embodiment of the invention is suitable for testing the signal quality of the DDR interface of the CPU chip, and because the DDR circuit is directly integrated on the mainboard and is not accessed through the connector, the influence introduced by the connector is eliminated, the maximum performance of the DDR interface of the CPU chip is conveniently tested, the signal quality can be better observed by using an oscilloscope, and the comparison research of the signal test and the performance test is realized. Simultaneously, the DDR circuit is integrated on the mainboard, the anti-vibration performance is stronger than that of the slot, and the system reliability is higher. The design method for integrating the RCD and DDR circuits on the motherboard can also be applied to the design that the DDR controller and the DDR particles need to be integrated on the same PCB, for example, the design method is applied to the high-reliability system design such as VPX (VPX is a next generation advanced computing platform standard established by VITA organization to meet the requirements of high reliability and high bandwidth in severe environment), the external DDR design of the CPU chip, the external DDR design of the FPGA, the embedded DDR design, and the like. The invention is not only applied to the test field, but also applied to the design of the actual product system.

Furthermore, the 18 DDR particles are designed by adopting a 2Rank, wherein the Rank refers to a 64-bit unit formed by a plurality of DDR particle data bits and selected to be accessed through a CS chip selection signal. For an ECC DIMM, a memory Rank has 72 data bits, including 64bits data +8bits ECC. In this embodiment, 18 DDR particles are numbered from 0 to 17 in sequence, and all even DDR particles form a first Rank, including DDR0, DDR2, DDR4, DDR6, DDR8, DDR10, DDR12, DDR14, and DDR16, which are marked as Rank0, and in the Rank0, DDR8 is an ECC particle. All odd DDR particles form a second Rank and comprise DDR1, DDR3, DDR5, DDR7, DDR9, DDR11, DDR13, DDR15 and DDR17 which are marked as Rank1, and DDR9 in the Rank1 is ECC particles.

Specifically to the layout and grouping, the first Rank is arranged in one column, the second Rank is arranged in one column, and 1 DDR grain located at the middle of each column is used to transmit an 8-bit ECC signal, and 8 DDR grains on both sides are used to transmit a 64-bit data signal. Specifically, the DDR0 and the DDR1 transfer data signals DQ [ 7: 0], DDR2 and DDR3 transmit data signals DQ [ 15: 8], DDR4 and DDR5 transfer data signals DQ [ 23: 16], DDR6 and DDR7 transmit data signals DQ [ 31: 24], DDR8 and DDR9 transfer data signals ECC [ 7: 0], DDR10 and DDR11 transmit data signals DQ [ 39: 32], DDR12 and DDR13 transfer data signals DQ [ 47: 40], DDR14 and DDR15 transfer data signals DQ [ 55: 48], DDR16 and DDR17 transfer data signals DQ [ 63: 56].

When the DDR particles are grouped, the two DDR particles used for transmitting the 8-bit ECC signal and the 8 DDR particles on one side of the DDR particles form the group A DDR particles, and the 8 DDR particles on the other side of the DDR particles used for transmitting the 8-bit ECC signal form the group B DDR particles. Namely DDR 8-17 is group A, DDR 0-7 is group B. The 18 DDDR particles are arranged on the front surface of the PCB, and DDR signal test points are arranged on the back surface of the PCB opposite to the 18 DDR particles. The design is convenient for testing the signal quality.

Similarly, the CPU chip is arranged on the front side of the PCB, and DDR interface signal test points are also arranged at corresponding positions on the back side of the CPU chip, so that the signal quality of the two transmitting and receiving ends of the test signal can be observed conveniently by using tools such as an oscilloscope and the like. The design method of the test point is DDR particles, a through hole is directly punched beside a pin of a CPU chip to the back, copper is exposed on the through hole on the back to serve as the test point, thus the signal quality is tested on the test point by using an oscilloscope, the distance from a probe of the oscilloscope to the actual pin of the chip is extremely short, and the signal waveform quality at the pin of the chip can be reflected. Fig. 2 shows a layout and test point distribution of a motherboard PCB. FIG. 2 shows the distribution of CPU, RCD and DDR 0-17, where the black dots inside the CPU, RCD and DDR 0-17 represent signal test points designed according to the pin distribution of the chip.

The above embodiment is 1DPC (1 RCD on 1 DDR circuit, i.e. 1 DDR circuit is connected to a DDR controller on the motherboard), 2Rank design, and may also be extended to 2DPC (2 DDR circuits are connected to a DDR controller on the motherboard), i.e. 2DPC, 1R design, or 2DPC, 2R design.

In addition, referring to fig. 3, besides the DDR interface externally connected to the DDR circuit, the CPU chip is further designed with the following interfaces:

2 PCIe x16 interfaces for connecting 2 PCIe x16 slots and allowing standard PCIe cards to be inserted;

4 SATA interfaces for connecting standard SATA disks;

the PCIe x2 interface is externally connected with a gigabit network chip I350, and the I350 is connected with a 2-path gigabit electric port network;

2 USB interfaces, and the integration supports USB2.0 and USB3.0 standards.

In addition, the motherboard is also integrated with a BMC (Baseboard management Controller) chip, and as a management unit of the motherboard, the motherboard is interconnected with the CPU through interfaces such as PCIe x1, lpc (low Pin count), USB, SPI (Serial Peripheral interface), and the like. The peripheral interfaces included in the BMC chip are as follows:

gigabit RJ45 interface: and the remote management interface is realized by externally connecting a BMC chip with a gigabit PHY chip. The remote management platform realizes the management of the mainboard through a gigabit network.

COM interface: a serial port interface;

VGA interface: the display interface is connected with the display equipment;

LED port 80: connecting a nixie tube and displaying the state of the CPU;

FAN CON [ 1: 8]: a fan control interface for controlling the rotation speed of the fan;

SD Card: the SD card interface is used for storing server log information;

the BMC FW (Firmware) is Firmware of the BMC system itself, and is stored in the BMC FW Flash.

The interconnection relationship between the BMC chip and the CPU chip comprises the following steps:

and (3) SPI interconnection: the CPU BIOS can Switch to BMC or CPU through SPI SW (Switch). When the BIOS firmware is upgraded, the BIOS firmware is switched to be connected to the BMC. And switching to the CPU when the computer is normally started up and operated. Therefore, CPU BIOS firmware can be upgraded through the remote management platform, namely the remote management platform sends a new BIOS to the BMC through a gigabit RJ45 interface of the BMC, the BMC writes a BIOS chip again, then the CPU is switched to through the SPI SW, and the CPU is started to use the new BIOS firmware.

LPC interconnection: and the LPC interface interconnected between the BMC and the CPU is used for transmitting the state information of the CPU starting operation, and after the state information is transmitted to the BMC, the state information is displayed through an LED PORT80 connected with the BMC. And meanwhile, the CPU is also connected to a CPLD (Complex Programmable Logic Device) to inform the CPLD of the current starting operation state of the CPU.

USB interconnection: the USB port interconnected between the BMC and the CPU is used for realizing a remote virtual machine, namely, the remote management platform is connected to the BMC through a BMC gigabit RJ45 network port and is connected to the CPU through the USB port of the BMC, so that the remote virtual machine is realized.

On the other hand, an embodiment of the present invention further provides an electronic device, which includes the motherboard of the above embodiment.

The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A motherboard is characterized in that the motherboard comprises a PCB board, a CPU chip and a DDR circuit are integrated on the PCB board, a DDR controller is arranged in the CPU chip,

2. The motherboard of claim 1, wherein the DDR circuit is implemented as an RDIMM.

3. The motherboard of claim 2 wherein the DDR circuit comprises two sets of DDR particles, RCD chips, and SPD chips, wherein,

4. The motherboard of claim 3, wherein the two groups of DDR particles comprise 18 DDR particles, one group comprises 10 DDR particles, 8 DDR particles are used for transmitting data signals, and 2 DDR particles are used for transmitting ECC signals; the other group includes 8 DDR grains for transmitting data signals.

5. The motherboard of claim 4, wherein the 18 DDDR particles are designed as 2 ranks, numbered sequentially from 0 to 17, all even DDR particles forming a first Rank, and all odd DDR particles forming a second Rank;

6. The motherboard of claim 5, wherein the 18 DDDR granules are arranged on the front surface of the PCB, and DDR signal test points are arranged on the back surface of the PCB opposite to the 18 DDR granules.

7. The main board according to claim 1, wherein the CPU chip is arranged on the front side of the PCB, a via hole is arranged beside the pin of the DDR interface, and the back side of the via hole is used as a DDR interface signal test point.

8. The motherboard of claim 1, wherein the CPU chip is further provided with interfaces comprising:

2 PCIe x16 interfaces for connecting 2 PCIe x16 slots;

4 SATA interfaces for connecting standard SATA disks;

a PCIe x2 interface for connecting one gigabit network chip I350;

2 USB interfaces.

9. The motherboard of claim 1, wherein a BMC chip is integrated on the PCB, and the BMC chip is interconnected with the CPU chip via an SPI interface, an LPC interface, and a USB interface.

10. An electronic device, characterized in that the electronic device comprises a motherboard as claimed in any one of claims 1 to 9.