TW202113385A - Boundary scan test system and method thereof - Google Patents

Abstract

A boundary scan test system and a method thereof are provided. Two ends of each first loopback circuit of each CPU test card are respectively connected to another CPU test card and a boundary scan unit of a DIMM test card, and each end of each second loopback circuit of each CPU test card is respectively connected to a boundary scan unit of a DIMM test card, so that multiple boundary scan nets are generated. A controller can execute a diagnostic program to select one of the boundary scan units to emit an excitation signal in each boundary scan net to make each of the other boundary scan units in each boundary scan net respectively receive a response signal, and then compare each response signal and its expected signal in each boundary scan net to output a diagnostic result for each boundary scan net.

Description

Boundary scan test system and method

The invention relates to a test system and method, in particular to a boundary scan test system and method.

On the server motherboard production line, the original motherboard CPU is used for boundary scan testing. It is necessary to plug and unplug the CPU every time a motherboard is tested. A large number of tests will cause damage to the CPU, making the CPU a test wear and tear. Since the original CPU on the motherboard is expensive, there is a problem of high test costs.

In view of this, the relevant industry began to develop CPU test cards based on the actual needs of the production line. However, because the size of the CPU test card needs to be consistent with the size of the original CPU, in the process of designing the CPU test card, it is necessary to face the challenge of how to configure test resources for thousands of pins to be tested under the size of the original CPU.

Therefore, the current CPU test cards on the market generally adopt a multi-chip design, and each test card covers only a part of the pins of the CPU socket. During the test, the test cards need to be replaced and tested one by one, and then the test results of the multiple chips are combined. Output test reports, but this method has problems such as time cost, test fixture design, test process control, etc. caused by frequent replacement of test cards, and is not suitable for production lines.

In summary, how to design a low-cost CPU test card that can assist the boundary scan test process of the production line according to the actual needs of the production line, and then design a better boundary scan test process, has always been an important research and development topic for related industries. one.

The invention discloses a boundary scan test system and method.

First, the present invention discloses a boundary scan test system for boundary scan testing of a motherboard under test. The motherboard under test includes a plurality of CPU sockets and a plurality of DIMM sockets. Multiple Quick Path Interconnect (QPI) lines are connected, and the CPU sockets and the DIMM sockets are connected through multiple input/output (I/O) lines. The boundary scan test system includes: multiple CPU test cards (test cards), multiple DIMM test cards and test control hosts. The CPU test cards are used to insert into the CPU sockets in a one-to-one manner. Each CPU test card includes a plurality of first loopback lines and a plurality of second loopback lines, and each of the first loopback lines of each CPU test card Both ends of a loopback line are respectively connected to a QPI line and an I/O line, and both ends of each second loopback line of each CPU test card are respectively connected to an I/O line. The DIMM test cards are used for inserting into the DIMM slots in a one-to-one manner, each DIMM test card includes at least one boundary scan unit, and at least one boundary scan unit of each DIMM test card is connected to an I/O line . The test control host is used to generate a plurality of boundary scan line nets according to the connection relationship between the CPU test cards, the DIMM test cards and the motherboard to be tested, and to execute the diagnostic program, so as to select any one in each boundary scan line net. One of the boundary scan units causes it to emit an excitation signal, and the other boundary scan units receive corresponding response signals, and compare each response signal in each boundary scan line network with its corresponding expected signal to output each boundary Scan the diagnosis result of the network.

In addition, the present invention discloses a boundary scan test method. The method includes the following steps: providing a motherboard to be tested, a plurality of CPU test cards, and a plurality of DIMM test cards, wherein the motherboard to be tested includes a plurality of CPU slots and a plurality of DIMM test cards. DIMM sockets, the CPU sockets are connected through multiple QPI lines, the CPU sockets and the DIMM sockets are connected through multiple input and output lines, and each CPU test card includes multiple first loops Circuit and multiple second loopback circuits, each DIMM test card includes at least one boundary scan unit; the CPU test cards are inserted in the CPU sockets in a one-to-one manner, so that each of the first Both ends of a loopback line are connected to a QPI line and an I/O line, so that both ends of each second loopback line of each CPU test card are respectively connected to an I/O line; plug-in in a one-to-one manner The DIMM test cards are connected to the DIMM slots, so that at least one boundary scan unit of each DIMM test card is connected to an I/O line; according to the connection of the CPU test cards, the DIMM test cards and the motherboard to be tested A plurality of boundary scan line nets are generated from the relationship; in each boundary scan line net, one of the boundary scan units is selected to emit an excitation signal, and the other boundary scan units receive corresponding response signals; and compare each Each response signal in the boundary scan line network and its corresponding expected signal are used to output the diagnosis result of each boundary scan line network.

The boundary scan test system and method disclosed in the present invention are as above. The difference from the prior art is that the present invention connects another CPU test card and a DIMM test card through both ends of the first loopback line of each CPU test card. Boundary scan unit, the two ends of the second loopback circuit of each CPU test card are respectively connected to the boundary scan unit of a DIMM test card to generate a plurality of boundary scan line nets; the test control host can execute the diagnostic program for each In the boundary scan line network, select one of the boundary scan units to send out an excitation signal, and the other boundary scan units respectively receive the corresponding response signals, and compare each response signal in each boundary scan line network with its corresponding expected signal, To output the diagnosis results of each boundary scan line network.

Through the above technical means, the CPU test card of the present invention can achieve basic coverage of the pins to be tested under the size of the original CPU, so as to save test resources to the greatest extent. There is no need to frequently replace the CPU test card during the boundary scan test process, and diagnosis The process is clear and convenient, and all faulty pins can be accurately covered.

The following describes the implementation of the present invention in detail with the drawings and embodiments, so as to fully understand and implement the implementation process of how the present invention uses technical means to solve technical problems and achieve technical effects.

Please refer to "Figure 1" first. "Figure 1" is a schematic structural diagram of an embodiment of the boundary scan test system of the present invention. In this embodiment, the boundary scan test system can be used to perform a boundary scan test on the motherboard under test 50. The motherboard under test 50 can include a plurality of central processing unit (CPU) slots 52 and a plurality of dual in-line Plug-in memory module (Dual In-Line Memory Modules, DIMM) sockets 54, these CPU sockets 52 are connected by multiple Quick Path Interconnect (QPI) lines, and these CPU sockets 52 It is connected to the DIMM sockets 54 through multiple input and output (I/O) lines. To avoid overly complicated description, in this embodiment, only two CPU sockets 52, eight DIMM sockets 54, ten I/O lines (as shown by the dashed line in "Figure 1"), and two QPI The route (as shown by the thick chain line in "Figure 1") is described, but this embodiment is not intended to limit the present invention, and can be adjusted according to actual conditions.

The boundary scan test system may include: a plurality of CPU test cards (test cards) 110, a plurality of DIMM test cards 120, a test access port (TAP) controller 60 and a test control host 130, the CPU test cards 110 is used to insert into the CPU sockets 52 in a one-to-one manner (the figure is only shown with a connecting line between the two), and the DIMM test cards 120 are used to insert into the CPU sockets 52 in a one-to-one manner. The DIMM slot 54 (the figure is only represented by a connecting line between the two). Therefore, the number of the CPU test card 110 in this embodiment is two, and the number of the DIMM test card 120 is eight. The test control host 130 can use the TAP controller 60 and the motherboard 50 to be tested to interact with the CPU test cards 110 inserted in the CPU sockets 52 and the DIMM sockets 54 These DIMM test cards 120 are connected to each other and transfer information and data to each other for boundary scan testing. It should be noted that the size of each CPU test card 110 needs to be consistent with the size of the original CPU, and the size of each DIMM test card 120 needs to be consistent with the size of the original DIMM.

Each CPU test card 110 may include a plurality of first loopback lines 114 and a plurality of second loopback lines 112. When each CPU test card 110 is inserted into the CPU slot 52, each CPU test card 110 will Both ends of a loopback line 114 can be respectively connected to a QPI line and an I/O line, and both ends of each second loopback line 112 of each CPU test card 110 can be respectively connected to an I/O line; each DIMM The test card 120 may include at least one boundary scan unit 122. When each DIMM test card 120 is inserted into the DIMM slot 54, at least one boundary scan unit 122 of each DIMM test card 120 may be connected to an I/O line. To avoid overly complicated description, in this embodiment, each CPU test card 110 may include a second loopback line 112 and two first loopback lines 114, and the six DIMM test cards 120 may include a boundary scan unit 122, and two Each DIMM test card 120 may include two boundary scan units 122, but this embodiment is not intended to limit the present invention, and can be adjusted according to actual conditions. Among them, each boundary scan unit 122 can be used as an excitation terminal or a response terminal.

The test control host 130 can generate a plurality of boundary scan line nets according to the connection relationship between the CPU test cards 110, the DIMM test cards 120 and the motherboard 50 under test. Wherein, each boundary scan line network includes a plurality of test path pins, and the test path pins included in each boundary scan line network are the pins through which the boundary scan path of the boundary scan line network passes, and may be CPUs. The connection pins on the socket 52 for connecting with the DIMM socket (that is, the pins for connecting the CPU socket 52 with the I/O line), the input and output pins on the DIMM socket 54 for connecting with the CPU socket 52 (I /O) pin (that is, the pin that connects the DIMM socket 54 to the I/O line).

In this embodiment, there are four boundary scan line nets. The boundary scan path of the first boundary scan line net can start from the end point g (that is, the boundary scan unit 122) and pass through the pin G (that is, the DIMM slot 54 and I/O line connection pin), pin M (that is, the pin connected to the CPU socket 52 and the I/O line), the second loopback line 112, and pin N (that is, the CPU socket 52 and the I/O line Connected pin) and pin H (that is, the pin connected to the DIMM socket 54 and the I/O line) until the end point h (that is, the other boundary scan unit 122), so the first boundary scan line network includes The test path pins are pin G, pin M, pin N, and pin H; the boundary scan path of the second boundary scan network can start from the end point e (that is, the boundary scan unit 122), Pass through pin E (that is, the pin connected to the DIMM socket 54 and the I/O line), pin O (that is, the pin connected to the CPU socket 52 and the I/O line), the first first loopback line 114, Pin R (the pin that connects the CPU socket 52 to another CPU socket 52), QPI line, pin S (the pin that connects the CPU socket 52 to another CPU socket 52), the second The first loopback line 114, pin V (that is, the pin connected to the CPU socket 52 and the I/O line), and pin F (that is, the pin connected to the DIMM socket 54 and the I/O line), until the endpoint f (That is, the boundary scan unit 122), so the test path pins included in the second boundary scan network are pin E, pin O, pin R, pin S, pin V, and pin F ; The boundary scan path of the third boundary scan line network can start from the endpoint a (that is, the boundary scan unit 122), and after passing through the pin A (that is, the pin connected to the DIMM slot 54 and the I/O line) is divided into Two sub-paths, the first sub-path is through pin C (that is, the pin connected to the DIMM slot 54 and the I/O line) and enters the endpoint c (that is, the boundary scan unit 122), and the second sub-path is through Pin P (that is, the pin that connects the CPU socket 52 to the I/O line), the first first loopback line 114, and pin Q (that is, the pin that connects the CPU socket 52 to another CPU socket 52) , QPI line, pin T (that is, the pin connecting the CPU socket 52 to another CPU socket 52), the second first loopback line 114 and pin U (that is, the CPU socket 52 is connected to the I/O line After passing through the pin U, it can pass through the pin D (that is, the pin connecting the DIMM slot 54 and the I/O line) to the end point d (that is, the boundary scan unit 122), and pass through the lead Pin B (that is, the pin connecting the DIMM slot 54 to the I/O line) enters the end point b (that is, the boundary scan unit 122), so the test path pins included in the third boundary scan network are Pin A, Pin P, Pin Q, Pin T, Pin U, Pin D, Pin B, and Pin C; the boundary scan path of the fourth boundary scan network can be from endpoint i (ie The boundary scan unit 122) starts and passes Pin I (that is, the pin connected to the DIMM socket 54 and the I/O line), pin W (that is, the pin connected to the CPU socket 52 and the I/O line), the second loopback line 112, and pin X ( That is, the pin connecting the CPU socket 52 to the I/O line) and pin J (that is, the pin connecting the DIMM socket 54 to the I/O line), until the end point j (that is, the boundary scan unit 122), so the first The test path pins included in the four boundary scan lines are pin I, pin W, pin X, and pin J.

The test control host 130 can execute a diagnostic program for each boundary scan line network, so that in each boundary scan line network, one of the boundary scan units 122 can be selected to make it emit an excitation signal, and the other boundary scan units 122 receive The corresponding response signal is compared with each response signal in each boundary scan line network and its corresponding expected signal to output the diagnosis result of each boundary scan line network. In other words, the test control host 130 can perform the boundary scan test according to the boundary scan path of each boundary scan line network, when one of the boundary scan units 122 in each boundary scan line network is selected as the excitation terminal to make it emit After the excitation signal, based on its boundary scan path, it can be expected to know the expected signal that other boundary scan units 122 (ie, the responding end) in the boundary scan network will receive. If the response signal received by a certain boundary scan unit 122 When it does not meet the expected signal it expects to receive, it indicates that the boundary scan line network has a faulty pin. The test control host 130 needs to further based on the test results of each boundary scan line network (that is, each boundary scan line network Response signal) to perform fault diagnosis to output the diagnosis results of each boundary scan line network. Among them, the diagnosis result is used to indicate whether the test path pins included in each boundary scan network are properly welded to the motherboard, and whether there is an open circuit or a short circuit or other faults.

Among them, the principles of fault diagnosis based on the test results of each boundary scan line network include: (1) When only one response signal in a boundary scan line network does not meet its corresponding expected signal, it will receive the one that does not meet its corresponding expected signal. A test path pin corresponding to the boundary scan unit of the response signal of the expected signal reports an error; (2) When all the response signals in a certain boundary scan line network do not meet the corresponding expected signals, the All the test path pins included in the boundary scan line network report errors; and (3) If multiple test paths in a certain boundary scan line network pass through a certain test path pin, confirm that the test path pin passes through Whether the test paths pass the test, if at least one of the test paths passing the test path pin passes the test, it means that the test path pin test passes; if all the test paths that pass the test path pin When the test fails, an error will be reported for the test path pin test.

Taking the third boundary scan line network of this embodiment as an example, when the end point a is selected as the excitation end to send out the excitation signal, if the end point b is only the response end, the response signal received does not conform to its corresponding The expected signal of the end point b corresponds to the test path pin (ie pin B) reported an error. At this time, since the response signal received by the end point d as the responding end matches its corresponding expected signal, the end The test path pins A, P, Q, T, U shared by point b and end point d will not report an error; if the response signal received by the end point c, which is only the responding end, does not meet its corresponding expected signal, then Report an error to the test path pin corresponding to the end point c (ie pin C); if the response signal received by the end point d that is only the responding end does not meet its corresponding expected signal, then the end point d corresponds to The connected test path pin (ie pin D) reports an error; if the response signal received by endpoint b and endpoint c as the response terminal does not meet their corresponding expected signal, then the endpoint b and endpoint c will be Correspondingly connected test path pins (ie pins B and C) report an error; if the response signals received by endpoint c and endpoint d as the responding end do not meet their corresponding expected signals, then endpoint c The test path pins (ie pins C and D) connected to the end point d report an error; if the response signals received by the end points b and d as the response end do not meet their corresponding expected signals, Since there are shared test path pins A, P, Q, T, U between endpoint b and endpoint d, except for the test path pins corresponding to the connection between endpoint b and endpoint d (ie pin B In addition to reporting errors with pin D), the shared test path pins A, P, Q, T, and U need to be reported as errors; if they are all endpoints of the responder (ie endpoint b, endpoint c, and endpoint d) If the response signal received does not meet the corresponding expected signal, all test path pins included in the boundary scan line network (ie, pin A, pin B, pin C, pin D, pin P, pin Q, pin T and pin U) report an error. Therefore, the test control host 130 can perform fault diagnosis based on the test result of the third boundary scan line network to output the diagnosis result of the boundary scan line network.

In addition, in this embodiment, each CPU test card 110 may be provided with at least one boundary scan chip 116. When each CPU test card 110 is inserted into the corresponding CPU socket 52, the at least one boundary scan chip 116 Multiple ground (GND) pins, multiple power (Power) pins, and multiple control input and output (Control I/O) pins of the CPU socket 52 can be connected. It should be noted that, in order to avoid overly complicated description, in this embodiment, each CPU test card 110 is provided with only one boundary scan chip 116, and each boundary scan chip 116 is connected to only one ground pin (ie pin m or pin m). Pin s), a power supply pin (ie pin n or pin t), and a control input and output pin (ie pin p or pin u) are connected, but this embodiment is not intended to limit the present invention.

In this embodiment, the test control host 130 can connect to the CPU test cards 110 inserted in the CPU sockets 52 through the TAP controller 60 and the host board 50 to be tested, and transmit information and data to each other. Boundary scan tests are performed on the ground pins, the power pins, and the control input and output pins.

In this embodiment, through the design of the first loopback line and the second loopback line of each CPU test card 110, each CPU test card 110 can cover all the QPI pins on each CPU socket 52 (ie, CPU The pins connecting the socket 52 to the QPI line) and the connecting pins between it and the DIMM socket (that is, the pins connecting the CPU socket 52 to the I/O line). Therefore, when the test control host 130 can use the TAP When the controller 60 performs boundary scan tests on these pins, the CPU test cards 110 do not need to provide boundary scan hardware resources, which reduces the test resources that need to be configured under the size of the original CPU. In addition, through the design of the boundary scan chip 116 provided on each CPU test card 110, each CPU test card 110 can cover part of the ground pins, power pins, and control input and output pins on each CPU socket 52 Therefore, when the test control host 130 can perform boundary scan tests on these pins through the TAP controller 60, the CPU test cards 110 are required to provide boundary scan hardware resources.

Taking the CPU test card of the present invention instead of the Haswell type CPU of Intel Corporation as an example, since the CPU socket corresponding to the Haswell type CPU has 3647 pins, the CPU test card of the present invention uses the first loopback line and the second loopback line. The design and setting of the boundary scan chip can basically cover the 166 ground pins, 76 power pins and 297 control input and output pins of the Haswell CPU, and can also cover all the QPI pins and connections on each CPU socket Pins (916 pins in total), therefore, the CPU test card of the present invention can be configured with a test coverage of 40% of all pins of the CPU socket under the size of the original CPU, so as to save test resources to the greatest extent. During the boundary scan test, there is no need to frequently replace the CPU test card, and the diagnosis process is clear and convenient, which can accurately cover all faulty pins.

Next, please refer to "Figure 2". "Figure 2" is a method flowchart of an embodiment of the boundary scan test method performed by the boundary scan test system of "Figure 1". In this embodiment, the boundary scan test method may include the following steps: providing a motherboard to be tested, a plurality of CPU test cards, and a plurality of DIMM test cards, wherein the motherboard to be tested includes a plurality of CPU sockets and a plurality of DIMM sockets. The CPU sockets are connected through multiple QPI lines, the CPU sockets and the DIMM sockets are connected through multiple input and output lines, and each CPU test card includes multiple first loopback lines and A plurality of second loopback lines, each DIMM test card includes at least one boundary scan unit (step 210); the CPU test cards are inserted in the CPU slots in a one-to-one manner, so that each CPU test card Both ends of a first loopback line are respectively connected to a QPI line and an I/O line, so that both ends of each second loopback line of each CPU test card are respectively connected to an I/O line (step 220); Insert the DIMM test cards into the DIMM slots in a one-to-one manner, so that at least one boundary scan unit of each DIMM test card is connected to an I/O line (step 230); according to the CPU test cards, the The connection relationship between the DIMM test card and the motherboard to be tested generates multiple boundary scan line nets (step 240); in each boundary scan line net, select one of the boundary scan units to emit an excitation signal, and the others The boundary scan unit receives the corresponding response signal (step 250); and compares each response signal in each boundary scan network with its corresponding expected signal to output the diagnosis result of each boundary scan network (step 260).

Through the above steps, you can connect another CPU test card and the boundary scan unit of a DIMM test card through both ends of the first loopback line of each CPU test card, and both ends of the second loopback line of each CPU test card Connect the boundary scan units of a DIMM test card respectively to generate multiple boundary scan line nets; the test control host can execute the diagnostic program to select one of the boundary scan units in each boundary scan line net to make it emit excitation Signals, other boundary scan units respectively receive corresponding response signals, and compare each response signal in each boundary scan line network with its corresponding expected signal to output the diagnosis result of each boundary scan line network.

Wherein, the test control host compares each response signal in each boundary scan line network with its corresponding expected signal to output the diagnosis result of each boundary scan line network. The step may include: when there is only one boundary scan line network When the response signal does not meet the corresponding expected signal, a test path pin corresponding to the boundary scan unit that receives the response signal that does not meet the corresponding expected signal reports an error, and then outputs the diagnosis result of the boundary scan line network; And when all the response signals in a certain boundary scan line network do not meet the corresponding expected signals, all the test path pins included in the boundary scan line network report an error, and then output the boundary scan The diagnosis result of the network. Among them, if multiple test paths in a certain boundary scan line network pass through a certain test path pin, it is confirmed whether the test paths passing through the test path pin are tested, and if the test paths pass the test path pins. When at least one of the paths has passed the test, it means that the test path pins have passed the test; if all the test paths passing through the test path pins have failed the test, the test path pin test error will be reported.

In addition, each CPU test card can be provided with at least one boundary scan chip. When each CPU test card is inserted into the corresponding CPU socket, the at least one boundary scan chip can be connected to multiple grounding leads of the CPU socket. Pins, multiple power pins, and multiple control input and output pins, so that the test control host performs boundary scan tests on the ground pins, the power pins, and the control input and output pins through the TAP controller. , Provide hardware resources required by boundary scan.

In summary, it can be seen that the difference between the present invention and the prior art is that the two ends of the first loopback line of each CPU test card are connected to the boundary scan unit of another CPU test card and a DIMM test card. The two ends of the second loopback line of the test card are respectively connected to the boundary scan unit of a DIMM test card to generate a plurality of boundary scan line nets; the test control host can execute the diagnostic program to perform any task in each boundary scan line net. Choose one of the boundary scan units to send out the excitation signal, and the other boundary scan units receive the corresponding response signals, and compare each response signal in each boundary scan line network with its corresponding expected signal to output each boundary scan line network With this technical means, the CPU test card of the present invention can save test resources to the greatest extent under the size of the original CPU. There is no need to replace the CPU test card frequently during the boundary scan test process, and the diagnosis process is clear and convenient. , Can accurately cover all faulty pins.

Although the present invention is disclosed in the foregoing embodiments as above, it is not intended to limit the present invention. Anyone familiar with similar art can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of patent protection shall be determined by the scope of the patent application attached to this specification.

50: motherboard to be tested 52: CPU socket 54: DIMM slot 60: TAP controller 110: CPU test card 112: The first loopback line 114: second loopback line 116: Boundary scan wafer 120: DIMM test card 122: Boundary Scan Unit 130: Test control host Step 210: Provide a motherboard to be tested, a plurality of CPU test cards and a plurality of DIMM test cards, wherein the motherboard to be tested includes a plurality of CPU sockets and a plurality of DIMM sockets, and a plurality of CPU sockets pass through The QPI lines are connected. The CPU sockets and the DIMM sockets are connected through a plurality of input and output lines. Each CPU test card includes a plurality of first loopback lines and a plurality of second loopback lines. Each DIMM test card Includes at least one boundary scan unit Step 220: Insert the CPU test cards in the CPU sockets in a one-to-one manner, so that the two ends of each first loopback line of each CPU test card are respectively connected to a QPI line and an I/O line. Connect the two ends of each second loopback line of each CPU test card to an I/O line respectively Step 230: Insert the DIMM test cards in the DIMM slots in a one-to-one manner, so that at least one boundary scan unit of each DIMM test card is connected to an I/O line Step 240: Generate a plurality of boundary scan line nets according to the connection relationship between the CPU test cards, the DIMM test cards and the motherboard to be tested Step 250: In each boundary scan line network, select one of the boundary scan units to emit an excitation signal, and the other boundary scan units receive corresponding response signals Step 260: Compare each response signal in each boundary scan line network with its corresponding expected signal to output the diagnosis result of each boundary scan line network

Figure 1 is a schematic structural diagram of an embodiment of the boundary scan test system of the present invention. FIG. 2 is a method flowchart of an embodiment of the boundary scan test method performed by the boundary scan test system of FIG. 1. FIG.

50: motherboard to be tested

52: CPU socket

54: DIMM slot

60: TAP controller

110: CPU test card

112: The first loopback line

114: second loopback line

116: Boundary scan wafer

120: DIMM test card

122: Boundary Scan Unit

130: Test control host

Claims (8)

A boundary scan test system for performing boundary scan testing on a motherboard to be tested. The motherboard to be tested includes a plurality of central processing unit (CPU) slots and a plurality of dual in-line memory modules. Group (Dual In-Line Memory Modules, DIMM) sockets, these CPU sockets are connected through multiple Quick Path Interconnect (QPI) lines, between the CPU sockets and the DIMM sockets Connected through multiple input and output (I/O) lines, the boundary scan test system includes: A plurality of CPU test cards (test cards) are used to be inserted into the CPU sockets in a one-to-one manner. Each CPU test card includes a plurality of first loopback lines and a plurality of second loopback lines. Both ends of each first loopback line of the CPU test card are respectively connected to one of the QPI line and one of the I/O lines, and both ends of each second loopback line of each of the CPU test cards are respectively connected to one of the two ends of the second loopback line. I/O lines; A plurality of DIMM test cards for inserting into the DIMM slots in a one-to-one manner, each of the DIMM test cards includes at least one boundary scan unit, and the at least one boundary scan unit of each DIMM test card is connected to one The I/O line; and A test control host is used to generate a plurality of boundary scan line nets according to the connection relationship between the CPU test cards, the DIMM test cards and the motherboard under test, and execute a diagnostic program to perform a diagnostic procedure on each of the boundary scan lines In the network, select one of the boundary scan units to emit an excitation signal, and the other boundary scan units receive a corresponding response signal, and compare each response signal in each boundary scan line network with its corresponding To output a diagnosis result of each boundary scan line network. According to the boundary scan test system described in item 1 of the scope of patent application, wherein each boundary scan line network includes a plurality of test path pins, and the test control host compares each response in each boundary scan line network The signal and the corresponding expected signal to output the diagnosis result of each boundary scan line network includes the following steps: When only one of the response signals in a certain boundary scan line network does not meet the corresponding expected signal, a test corresponding to the boundary scan unit that receives the response signal that does not meet the corresponding expected signal will be received The path pin reports an error, and then outputs the diagnosis result of the boundary scan line network; Wherein, if multiple test paths in a certain boundary scan line network pass through a certain test path pin, it is confirmed whether the test paths passing through the test path pin pass the test, if the test path passing through the test path pin When at least one of the test paths passes the test, it means that the test path pins pass the test; if all the test paths passing through the test path pins fail the test, an error is reported for the test path pins. According to the boundary scan test system described in item 1 of the scope of patent application, wherein each boundary scan line network includes a plurality of test path pins, and the test control host compares each response in each boundary scan line network The signal and the corresponding expected signal to output the diagnosis result of each boundary scan line network includes the following steps: When all the response signals in a certain boundary scan line network do not meet the corresponding expected signals, all the test path pins included in the boundary scan line network report an error, and then output the boundary scan The diagnosis result of the network; Wherein, if multiple test paths in a certain boundary scan line network pass through a certain test path pin, it is confirmed whether the test paths passing through the test path pin pass the test, if the test path passing through the test path pin When at least one of the test paths passes the test, it means that the test path pins pass the test; if all the test paths passing through the test path pins fail the test, an error is reported for the test path pins. According to the boundary scan test system described in item 1 of the scope of patent application, wherein each CPU test card is provided with at least one boundary scan chip, and when each CPU test card is inserted into the corresponding CPU slot, The at least one boundary scan chip is connected to a plurality of ground (GND) pins, a plurality of power (Power) pins and a plurality of control input and output (Control I/O) pins of the CPU socket. A boundary scan test method, which includes the following steps: Provide a motherboard under test, multiple CPU test cards and multiple DIMM test cards, where the motherboard under test includes multiple CPU slots and multiple DIMM slots, and multiple QPIs are passed between the CPU slots The CPU sockets and the DIMM sockets are connected through a plurality of input and output lines. Each CPU test card includes a plurality of first loopback lines and a plurality of second loopback lines, and each DIMM test card includes a plurality of first loopback lines and a plurality of second loopback lines. The card includes at least one boundary scan unit; Insert the CPU test cards in the CPU slots in a one-to-one manner, so that the two ends of each first loopback line of each CPU test card are respectively connected to one QPI line and one I/O line , So that both ends of each second loopback line of each CPU test card are respectively connected to one I/O line; Inserting the DIMM test cards in the DIMM slots in a one-to-one manner, so that the at least one boundary scan unit of each DIMM test card is connected to the I/O line; Generating a plurality of boundary scan line nets according to the connection relationship between the CPU test cards, the DIMM test cards and the motherboard to be tested; In each boundary scan line network, select one of the boundary scan units to send out an excitation signal, and the other boundary scan units receive a corresponding response signal; and Compare each response signal in each boundary scan line network with a corresponding expected signal to output a diagnosis result of each boundary scan line network. According to the boundary scan test method described in item 5 of the scope of patent application, wherein each boundary scan line network includes a plurality of test path pins, and each of the response signals in each boundary scan line network is compared with its corresponding The step of outputting the diagnosis result of each boundary scan line network of the expected signal includes: When only one of the response signals in a certain boundary scan line network does not meet the corresponding expected signal, a test corresponding to the boundary scan unit that receives the response signal that does not meet the corresponding expected signal will be received The path pin reports an error, and then outputs the diagnosis result of the boundary scan line network; Wherein, if multiple test paths in a certain boundary scan line network pass through a certain test path pin, it is confirmed whether the test paths passing through the test path pin pass the test, if the test path passing through the test path pin When at least one of the test paths passes the test, it means that the test path pins pass the test; if all the test paths passing through the test path pins fail the test, an error is reported for the test path pins. According to the boundary scan test method described in item 5 of the scope of patent application, wherein each boundary scan line network includes a plurality of test path pins, and each of the response signals in each boundary scan line network is compared with its corresponding The step of outputting the diagnosis result of each boundary scan line network of the expected signal includes: When all the response signals in a certain boundary scan line network do not meet the corresponding expected signals, all the test path pins included in the boundary scan line network report an error, and then output the boundary scan The diagnosis result of the network; Wherein, if multiple test paths in a certain boundary scan line network pass through a certain test path pin, it is confirmed whether the test paths passing through the test path pin pass the test, if the test path passing through the test path pin When at least one of the test paths passes the test, it means that the test path pins pass the test; if all the test paths passing through the test path pins fail the test, an error is reported for the test path pins. According to the boundary scan test method described in item 5 of the scope of patent application, at least one boundary scan chip is arranged on each of the CPU test cards, and when each of the CPU test cards is inserted into the corresponding CPU slot, The at least one boundary scan chip is connected to multiple ground pins, multiple power pins, and multiple control input and output pins of the CPU socket.

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