TW201710699A - Detecting apparatus for CPU slot connection of motherboard based on boundary scan and method thereof - Google Patents

Abstract

A detecting apparatus for CPU slot connection of motherboard based on boundary scan and a method thereof are provide. In the method, analysis a circuit diagram of a test motherboard and a boundary scan description language file of the CPU, and download scan chains information of the test motherboard. Following up, download a scan unit information according to a CPU slot of the test motherboard. Guide the CPU enters a boundary scan mode through the tap controller based on a test controller. Executing various types of boundary scan subtests, than collect and analyze response results. Then, it is determines whether the test motherboard isn't fault and positioning a fault position based on the response results.

Description

Method and device for testing connection of motherboard CPU socket based on boundary scan

The invention relates to the field of computer motherboard testing, in particular to a method and a device for testing a motherboard CPU socket based on boundary scan.

Testing of the connection of individual chip devices on the computer motherboard has been one of the focus of the industry's search for efficiency. Among them, the connection test of the CPU socket has always been a difficult point. Due to the high CPU pin density and the stylus on the slot are tilted, it cannot be tested with the lower ejector pin. At present, the industry's connection test for CPU sockets usually adopts the following two test schemes.

The first test scenario is to plug in the CPU, boot the system, and test the connection by performing a functional test. The disadvantage of this test scheme is that the functional test cannot be accurate to the pin connectivity level, especially for differential signals, the open/short fault of a single line is difficult to show.

Another test solution is to use the fixture to turn the CPU pins out and focus on the connectivity test. The disadvantages of this test scheme are: (1) Due to the large number of CPU pins, the number of pins to be transferred from a single fixture is limited. To test one CPU socket, multiple fixtures are required, and each fixture completes testing of a part of the pins. And need to power off when replacing the fixture. (2) For different packaged CPUs, for example, LGA1155, LGA1356, LGA1567, LGA2011, need to make different fixtures. (3) The fixture has very high requirements on the production process and is difficult to manufacture. (4) Due to the manufacturing process, the fixture has limited pinout. Even with multiple fixtures, the test coverage is still very low, usually only about 11%.

A brief summary of the invention is set forth below in order to provide a basic understanding of certain aspects of the invention. It should be understood that this summary is not an exhaustive overview of the invention. It is not intended to identify key or critical aspects of the invention, and is not intended to limit the scope of the invention. Its purpose is to present some concepts in a simplified form as a pre-

In view of the above disadvantages and limitations of the prior art, the present invention provides a connection test method for a motherboard CPU socket based on boundary scan. The method includes the following steps: analyzing a circuit diagram of a motherboard to be tested and a boundary scan description language file of the motherboard CPU, and extracting Scanning chain information of the motherboard to be tested; extracting the scanning unit information corresponding to the CPU socket connection line of the motherboard to be tested; controlling the CPU of the motherboard to be tested to enter the boundary scan mode through the TAP controller on the test control host; running multiple types The boundary scan subtest tests, collects and analyzes the response result; according to the response result, determines whether the motherboard to be tested has a fault and locates the fault location.

The invention also provides a connection test device for a motherboard scan based on a boundary scan, the connection test device includes: a test control host, a TAP controller, and a motherboard to be tested; the motherboard to be tested includes a motherboard CPU, and the motherboard CPU can work Boundary scan mode; the test control host is used to send test instructions and test data to the TAP controller; the TAP controller is used to convert the test data and test commands into JTAG signals and send them to each scan chain on the motherboard to be tested, and scan the chain Response The material is sent to the test control host for collection and analysis; the main CPU is used to operate in the boundary scan mode according to the received JTAG signal, and responds to the test data to feed back the scan chain response data to the TAP controller; the test control host determines whether the motherboard CPU slot is There is a connection failure and the location of the fault is located.

The connection test device and method for the boundary scan based motherboard CPU socket according to the present invention do not need to design and manufacture the CPU signal transfer fixture, even if the virtual DIMM fixture and the virtual PCIE fixture are required, the fixture design or the manufacturing process are It's simpler. During the test, there is no need to switch the hardware off after power-off. After one hardware plug-in is completed, all tests are completed at one time. Test efficiency is improved and the entire test can be completed in 30 seconds. Moreover, the connection test is a pin-connected level test that accurately pinpoints connection faults to pins and greatly improves test coverage.

1‧‧‧Test Control Host

2‧‧‧TAP controller

3‧‧‧Motherboard to be tested

4‧‧‧ motherboard CPU

5‧‧‧ DIMM slot

6‧‧‧PCIE slot

7‧‧‧CPU slot

8‧‧‧Virtual DIMM fixture

9‧‧‧Virtual PCIE fixture

10‧‧‧USB connection埠

The above and other objects, features and advantages of the present invention will become more <RTIgt; The components in the figures are merely illustrative of the principles of the invention. In the drawings, the same or similar technical features or components will be denoted by the same or similar reference numerals.

1 is a block diagram showing the structure of a connection test apparatus for a boundary scan based motherboard CPU socket according to an embodiment of the present invention; and FIG. 2 is a diagram showing a boundary scan based motherboard CPU according to an embodiment of the present invention. Flowchart of the socket test method.

Embodiments of the present invention will now be described with reference to the accompanying drawings. In the invention Elements and features described in one figure or embodiment may be combined with elements and features illustrated in one or more other figures or embodiments. It should be noted that, for the sake of clarity, representations and descriptions of components and processes known to those of ordinary skill in the art that are not related to the present invention are omitted from the drawings and the description.

1 is a block diagram showing the structure of a connection test apparatus for a boundary scan based motherboard CPU socket according to an embodiment of the present invention. The connection test device includes: a test control host 1, a TAP controller (test access controller) 2, and a motherboard 3 to be tested. The motherboard 3 to be tested includes a motherboard CPU 4, a DIMM slot 5, and a PCIE slot 6, and the motherboard CPU 4, DIMM slot 5, and PCIE slot 6 both support the boundary scan mode. During the test, the CPU socket 4 of the motherboard 3 to be tested is plugged into the motherboard CPU 4, and the DIMM slot 5 and the PCIE slot 6 can be respectively inserted into the virtual DIMM fixture 8 and the virtual PCIE fixture 9 through the test CPU plug. The connection of the slot 7 to the virtual DIMM fixture 8 and the virtual PCIE fixture 9 performs a connection test of the CPU socket 7. The test control host 1 is connected to the TAP controller 2 through the USB interface 10, and inputs test data. All test data generation, scheduling, result collection, and analysis are run in software on the test control host 1. The test control host 1 can be a personal computer (referred to as a PC), a server or a workstation. The TAP controller 2 is responsible for converting the test data sent by the test control host 1 through the USB interface 10 into a JTAG signal and transmitting it to each scan chain on the motherboard 3 to be tested, and transmitting the JTAG response signal to the test control host 1 for collection and analysis. The CPLD component (not shown) controls the power-on of the motherboard 3 to be tested, and supplies power to the virtual DIMM fixture 8 and the virtual PCIE fixture 9. The motherboard CPU 4, the virtual DIMM fixture 8 and the virtual PCIE fixture 9 operate in the boundary scan mode according to the received JTAG command signal, and feed back the scan chain response data to the TAP controller 2. The test control host 1 analyzes the response data, determines whether there is a connection failure in the CPU socket 7, and locates the fault location. Test control host 1 and TAP The controller 2 can also be connected by other communication methods, such as RS-232, RS-485, and the like.

2 is a flow chart showing a method for testing a connection of a motherboard scan based on a boundary scan according to an embodiment of the present invention. Take the Xeon E5-2620v3 CPU plugged into the server DL360G9 as an example. This test method is also applicable to other server models and other CPU models.

The CPU connected to the server DL360G9 is packaged in LGA2011. It contains 2011 pins. The pins can be divided into the following types: memory channel (direct connection between CPU and DDR). Pin: 656; fast channel interconnection (referred to as QPI, which refers to the direct connection between two CPUs): 168 pins, which can be divided into 84 groups of DC-coupled differential signals; DMI (capacitor connection between CPU and PCH): 16 pins, which can be divided into 8 groups of AC coupling Differential signal; PCI (capacitor connection between CPU and PCIE slot) Pin: 160, can be divided into 80 groups of AC-coupled differential signals; Reserved (referred to as Reserved, its not connected) Pins: 80; Control input and output ( CPU control signals to various external circuits) Pins: 67; Power (Power) pins: 233; and Ground (GND) pins: 631.

Among the above pins, except Power and GND can not be tested by boundary scan means, the remaining 1147 pins can be tested, accounting for 57% of the total pin count of the CPU.

In order for the connection test to cover all of the above measurable pins, a variety of boundary scan test types are required. Each test type serves as a subtest of the entire CPU socket test scheme, covering a portion of the pins, and multiple subtest sequences are executed in sequence. The types of subtests involved are:

(1) Scan chain integrity test: Check whether the multiple scan chains of the motherboard are stable and effective.

(2) Pin sampling test: Check whether the current value of the CPU pin meets the preset, including testing the following pins, for example, part of the control input and output pins, including the part of the pin that is directly pulled up/down and check the power status. Part of the value of the pin.

(3) Direct Connected Test: Follow the 1149.1 specification (full specification name?), which includes the following pins, memory channel pins, QPI pins, and some control input and output pins. For example, the CPU is directly connected to the control pins of the PCH and CPLD components.

(4) Self-excitation self-response mode test: including testing of the Reserved pin. For example, to test Reserved pin A, assume that A is a net, and both the stimulus and the responder are A. It is possible to test if pin A is short-circuited with the rest of the net.

(5) Differential Interconnect Test: Follows the IEEE 1149.6 specification, including DMI pins and PCI pins.

During the test, the circuit diagram of the motherboard 3 to be tested is first analyzed, and the connection information of the CPU socket 7 is extracted. Then, the boundary scan description language file of the motherboard CPU 4, the virtual DIMM fixture 8 and the virtual PCIE fixture 9 on the motherboard 3 to be tested is analyzed, and the scan chain information S201 on the motherboard 3 to be tested is extracted. According to the scan chain information, the scan unit information S202 of the main board CPU4, the virtual DIMM jig 8, and the virtual PCIE jig 9 is extracted. The test program 1 causes the test program to control the main board CPU 4 and the virtual DIMM fixture 8 and the virtual PCIE jig 9 to enter the boundary scan mode S203 through the TAP controller 2. According to the above multiple boundary scan subtest types, connection tests are performed on all measurable pins, and the response result S204 is collected and analyzed. During the above test, the motherboard 3 to be tested needs to be plugged into the motherboard CPU 4, and the virtual DIMM fixture 8 and the virtual PCIE fixture 9. Based on the response result, it is judged whether or not there is a fault and the fault location S205 is located.

The above test method has the following advantages: there is no need to design and manufacture a CPU signal transfer jig, although the virtual DIMM jig 8 and the virtual PCIE jig 9 are also required, but the design and manufacturing process of the jig are relatively simple. During the test, there is no need to switch the hardware off after power-off. After one hardware plug-in is completed, all tests are completed at one time. Test efficiency is improved and the entire test can be completed in 30 seconds. Moreover, the connection test is a pin-connected level test that accurately locates the connection fault to the pin. The use of boundary scan also greatly improves test coverage and can cover about 57% of CPU pins.

In the above embodiment, although the virtual DIMM and the virtual PCIE are used as connection test components with the CPU socket, they are not limited to the virtual DIMM and the virtual PCIE. It is also possible to use other chip slot components on the motherboard to be tested as the connection test component as long as the scan chain satisfies the scan chain connection test capable of plugging the CPU cable with the motherboard to be tested.

It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not limited thereto; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that The technical solutions described in the foregoing embodiments are modified, or the equivalents of the technical features are replaced. The modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

1‧‧‧Test Control Host

2‧‧‧TAP controller

3‧‧‧Motherboard to be tested

4‧‧‧ motherboard CPU

5‧‧‧ DIMM slot

6‧‧‧PCIE slot

7‧‧‧CPU slot

8‧‧‧Virtual DIMM fixture

9‧‧‧Virtual PCIE fixture

10‧‧‧USB connection埠

Claims (7)

A connection test method for a motherboard CPU socket based on boundary scan, the connection test method includes the following steps: analyzing a circuit diagram of a motherboard to be tested and a boundary scan description language file of the motherboard CPU, extracting scan chain information of the motherboard to be tested; extracting the Scanning unit information corresponding to the CPU socket connection line of the motherboard to be tested; controlling the CPU of the motherboard to be tested to enter the boundary scan mode through the TAP controller on the test control host; running various types of boundary scan subtests, collecting and analyzing a response result; and determining, according to the response result, whether the motherboard to be tested has a fault and locating the fault location. The connection test method of claim 1, wherein the connection test method further comprises: inserting a virtual DIMM fixture and a virtual PCIE fixture on the DIMM slot and the PCIE slot of the motherboard to be tested during the test, the test The mainboard CPU, the virtual DIMM fixture, and the virtual PCIE jig that control the main board to be tested through the TAP controller enter the boundary scan mode. The connection test method of claim 1, wherein the plurality of types of boundary scan subtests include: scan chain integrity test, pin sampling test, direct connection interconnection test, self-excitation self-response mode test, and differential interconnection test. A connection test device for a motherboard CPU socket based on boundary scan, the connection test device includes: a test control host, a TAP controller, and a motherboard to be tested; the motherboard to be tested includes a motherboard CPU, and the motherboard CPU can work in a boundary scan mode ; In the connection test, the test control host is configured to send test instructions and test data to the TAP controller, and the TAP controller is configured to convert the test data and the test command into JTAG signals and send them to each of the motherboards to be tested. Scanning the chain, and sending the response data of each scan chain to the test control host for collection and analysis, the motherboard CPU is configured to operate in the boundary scan mode according to the received JTAG signal, and respond to the test data to the TAP controller The feedback data of the scan chain is returned, and the test control host is also used to determine whether there is a connection failure in the CPU socket and locate the fault location. The connection test device of claim 4, wherein the motherboard to be tested is further connected with a virtual DIMM fixture and a virtual PCIE fixture for connecting to the DIMM slot and the PCIE slot respectively, and The TAP controller controls the motherboard CPU of the motherboard to be tested, the virtual DIMM fixture, and the virtual PCIE fixture to enter a boundary scan mode. The connection test device of claim 4 or 5, wherein the connection test device is configured to perform a boundary scan subtest on the motherboard to be tested, including: scan chain integrity test, pin sampling test, direct connection test, Self-energizing self-response mode testing and differential interconnect testing. The connection test device of claim 4, 5 or 6, wherein the connection test device further comprises a USB interface, and the test control host communicates with the TAP controller through the USB interface.