TWI785923B - Jtag adapter circuit board - Google Patents

Abstract

A JTAG adapter circuit board is provided. Foolproof mechanism is set at JTAG slot of JTAG adapter circuit board to provide each signal pin of JTAG slot is fixed location. Signal pin definition is not verified when connection interface transform to improve signal transmission efficiency. Therefore, the improve efficiency of JTAG interface transform signal may be achieved.

Description

JTAG transfer board

An adapter circuit board, in particular a JTAG adapter circuit board which can omit the definition and verification of signal pins during interface conversion of a joint test workgroup to improve signal transmission efficiency.

The existing connection interface conversion circuit board provides the conversion of different connection interfaces. When the conversion of different connection interfaces is performed through the connection interface conversion circuit board, it is necessary to define the signal pins because of the different definitions of pins for different connection interfaces. The verification of the signal pin definition will affect the efficiency of field connection. In addition, the original connection interface without a matching circuit will also affect the efficiency of signal transmission.

To sum up, it can be seen that the existing conversion circuit boards have long existed in the prior art because of the need for signal pin definition verification to affect the efficiency of on-site connection, and the lack of a matching circuit on the original connection interface will also affect the signal transmission efficiency. Therefore, it is necessary to propose Improved technical means to solve this problem.

In view of the problems existing in the prior art that the conversion circuit board needs to carry out signal pin definition verification to affect the field connection efficiency and the original connection interface without a matching circuit will also affect the signal transmission efficiency, the present invention discloses a JTAG conversion circuit board, in which :

The JTAG transfer circuit board disclosed by the present invention includes: a C-type universal serial bus (Universal Serial Bus, USB Type-C) slot and a joint test work group (Joint Test Action Group, JTAG) slot JTAG transfer board.

The C-type universal serial bus slot of the JTAG transfer circuit board includes the upper row of pin groups and the lower row of pin groups. The upper row of pin groups has the upper row of test data input (Test Data In, TDI) pins, The upper test data output (Test Data Out, TDO) pin, the upper test clock (Test Clock, TCK) pin, the upper test mode selection (Test Mode Select, TMS) pin, multiple upper ground (Ground , GND) pins, the lower row pin group has lower row test data input pins, lower row test data output pins, lower row test clock pins, lower row test mode selection pins and multiple lower row grounding pins bit.

The Joint Test Action Group (JTAG) slot of the JTAG transfer circuit board, the Joint Test Action Group slot has buckle fixing parts on the left and right sides, a fool-proof empty slot, and ten pins. There are two rows up and down and each row has five pins. Among the pins, the test clock pin, test mode selection pin, test data input pin, test data output pin and ground pin are fixed pins. Location.

Among them, the test clock pins are electrically connected to the upper test clock pins and the lower test clock pins, and the test mode selection pins are electrically connected to the upper test mode selection pins and the lower test mode selection pins respectively. The test data input pins are electrically connected to the upper row of test data input pins and the lower row of test data input pins, and the test data output pins are respectively connected to the upper row of test data output pins and the lower row of test data The output pins are electrically connected, and the grounding pins are respectively electrically connected to the upper row of grounding pins and the lower row of grounding pins.

The difference between the circuit board disclosed by the present invention and the prior art is that the position of each signal pin in the joint test work group slot is fixed by designing a fool-proof mechanism in the joint test work group slot. In order to improve the signal transmission efficiency, the verification of the signal pin definition can be omitted when realizing the interface conversion of the joint test work group.

Through the above-mentioned technical means, the present invention can achieve the technical effect of improving the transmission efficiency of the interface conversion signal of the joint test working group.

The implementation of the present invention will be described in detail below in conjunction with the drawings and examples, so that the realization process of how to use technical means to solve technical problems and achieve technical effects in the present invention can be fully understood and implemented accordingly.

The JTAG adapter circuit board disclosed by the present invention will be explained firstly below, and please refer to "Fig. 1", which is a circuit board block diagram of the JTAG adapter circuit board of the present invention.

The JTAG transfer circuit board disclosed in the present invention includes: a JTAG transfer circuit board 10 having a C-type universal serial bus slot 11 and a joint test working group slot 12 .

Please refer to "Fig. 2", which is a schematic diagram of the pin position of the C-type universal serial bus slot of the JTAG transfer circuit board of the present invention.

The C-type universal serial bus slot 11 of the JTAG adapter circuit board 10 includes an upper row of pins 111 and a lower row of pins 112, and the upper row of pins 111 has an upper row of test data input (Test Data In, TDI) pin 1111, upper test data output (Test Data Out, TDO) pin 1112, upper test clock (Test Clock, TCK) pin 1113, upper test mode selection (Test Mode Select, TMS) pin 1114, a plurality of upper row ground (Ground, GND) pins 1115, the lower row pin group 112 has lower row test data input pins 1121, lower row test data output pins 1122, lower row test clock pins 1123, The lower row of test mode selection pins 1124 and a plurality of lower row of ground pins 1125 .

The upper pin group 111 has twelve pins. The pin order of the upper pin group 111 is configured from right to left. The upper row of test data input pins 1111, the upper row of test data output pins 1112, the upper row of The test clock pin 1113 and the upper test mode selection pin 1114 are respectively the sixth pin, the seventh pin, the second pin and the eleventh pin of the upper pin group 111, and the upper pin group 111 The rest of the pins are all ground pins 1115 in the upper row.

The lower pin group 112 has twelve pins. The pin order of the lower pin group 112 is configured from left to right. The lower row of test data input pins 1121, the lower row of test data output pins 1122, the lower row of pins The test clock pin 1123 and the lower test mode selection pin 1124 are respectively the sixth pin, the seventh pin, the second pin and the eleventh pin of the lower pin group 112, and the lower pin group 112 The rest of the pins are ground pins 1125 in the lower row.

Please refer to "Fig. 1" and "Fig. 3". "Fig. 3" is a schematic diagram of the socket pins of the joint test working group of the JTAG transfer circuit board of the present invention.

The joint test work group slot 12 of the JTAG transfer circuit board 10, the joint test work group slot 12 has the buckle fixing parts 121 on the left and right sides, the anti-fooling empty slot 122 and ten pin positions, and the pin positions are up and down. Two rows and each row has five pins, the test clock pin 124, the test mode selection pin 125, the test data input pin 126, the test data output pin 127 and the ground pin 128 in the pins are fixed foot position.

It is worth noting that the five pins in the upper row in the joint test working group slot 12 are all ground pins 128, and the five lower row pins in the joint test working group slot 12 are respectively from right to left The test clock pin 124 , the test mode selection pin 125 , the test data input pin 126 , the test data output pin 127 and the empty pin 129 .

The joint test working group slot 12 and the test access port (Test Access Port, TAP) of the test access controller are made of polymer material, and the buckle fixing part 121 and the fool-proof empty slot 122 are provided for testing The test access port of the access controller is fixedly used with the joint test working group slot 12, and the test access port of the test access controller is provided with a first protruding anti-fool corresponding to the fool-proof empty slot 122 part and the second protruding anti-fooling part corresponding to the snap-on fixing part 121, the snap-on fixing part 121 and the second protruding anti-fooling part present the same geometric shape, and the size of the second protruding anti-fooling part is less than or equal to The size of the buckle fixing part 121, when the test access port of the test access controller is inserted into the joint test working group slot 12 to form an electrical connection, the buckle fixing part 121 and the second foolproof part are connected together. The buckle fixing between the test access port of the test access controller and the joint test working group slot 12 is fixed, and the foolproof empty slot 122 and the first protruding foolproof part Cooperating with each other provides the function of fool-proof insertion between the test access port of the test access controller and the joint test workgroup slot 12 .

The test clock pins 124 are electrically connected to the upper test clock pins 1113 and the lower test clock pins 1123 respectively, and the test mode selection pins 125 are respectively connected to the upper test mode selection pins 1114 and the lower test mode selection pins. The bit 1124 forms an electrical connection, the test data input pin 126 forms an electrical connection with the upper row of test data input pins 1111 and the lower row of test data input pins 1121, and the test data output pin 127 is respectively connected with the upper row of test data The output pins 1112 are electrically connected to the lower row of test data output pins 1122 , and the ground pins 128 are electrically connected to the upper row of ground pins 1115 and the lower row of ground pins 1125 .

Please refer again to "Fig. 1", the JTAG adapter circuit board 10 further has a set of positioning grooves 13 at left and right relative positions. The positioning grooves 13 provide a testing platform for the JTAG adapter circuit board 10 and the testing machine. The fixed positioning and anti-fooling, the detection platform of the detection machine is made of Bakelite material, metal material, etc., which is only used as an example and does not limit the scope of application of the present invention.

The C-type universal serial bus socket is used to provide and test the electrical connection of the dual in-line memory module (Dual In-line Memory Module, DIMM) socket fixture, and the joint test work group provides and tests the socket It is used for the electrical connection of the test access port (Test Access Port, TAP) of the access controller.

In summary, it can be seen that the difference between the present invention and the prior art lies in that the position of each signal pin in the joint test work group slot is fixed by designing a fool-proof mechanism in the joint test work group slot. When implementing joint test workgroup interface conversion, the verification of signal pin definition can be omitted to improve signal transmission efficiency.

This technical means can solve the problem in the prior art that the existing conversion circuit board needs to verify the signal pin definition and affect the signal transmission efficiency, so as to achieve the technical effect of improving the interface conversion signal transmission efficiency of the joint test work group.

Although the embodiments disclosed in the present invention are as above, the content described above is not intended to directly limit the patent protection scope of the present invention. Anyone with ordinary knowledge in the technical field to which the present invention belongs can make some changes in the forms and details of the implementation without departing from the disclosed spirit and scope of the present invention. The scope of patent protection of the present invention must still be defined by the appended patent application scope.

10: JTAG transfer circuit board

11: Type C universal serial bus socket

111: Upper row foot group

1111: Upper test data input pin

1112: Upper test data output pin

1113: Upper row test clock pin

1114: Upper test mode selection pin

1115: Upper row ground pin

112: Lower row foot group

1121: Lower test data input pin

1122: Lower test data output pin

1123: Lower test clock pin

1124: Lower test mode selection pin

1125: Lower row ground pin

12:Joint test workgroup slot

121: buckle fixing part

122: Anti-fool empty slot

124: Test clock pin in pin

125: Test mode selection pin

126: Test data input pin

127: Test data output pin

128: Ground pin

13: positioning groove

Figure 1 is a circuit board block diagram of the JTAG adapter circuit board of the present invention. FIG. 2 is a schematic diagram of the pin position of the C-type universal serial bus socket of the JTAG switching circuit board of the present invention. FIG. 3 is a schematic diagram of the socket pins of the joint test working group of the JTAG switching circuit board of the present invention.

10: JTAG transfer circuit board

11: Type C universal serial bus socket

12:Joint test workgroup slot

121: buckle fixing part

122: Anti-fool empty slot

13: positioning groove

Claims (7)

A kind of JTAG transfer circuit board, it comprises: a C type universal serial bus (Universal Serial Bus, USB Type-C) slot comprises upper row pin group and lower row pin group, described upper row pin group There is an upper row of test data input (Test Data In, TDI) pins, an upper row of test data output (Test Data Out, TDO) pins, an upper row of test clock (Test Clock, TCK) pins, an upper row of A row of test mode selection (Test Mode Select, TMS) pins and a plurality of upper row grounding (Ground, GND) pins, the lower row of pins has a lower row of test data input pins and a lower row of test data output pins bit, the lower row of test clock pins, the lower row of test mode selection pins and a plurality of lower row ground pins; and a joint test work group (Joint Test Action Group, JTAG) slot, the joint test work group The slot has buckle fixing parts on the left and right sides, a fool-proof empty slot and ten pin positions. The pin positions are in two rows up and down and each row has five pin positions. The joint test working group slot The five pins in the upper row are all ground pins, and the five pins in the lower row in the joint test working group slot are respectively a test clock pin, a test mode selection pin, and a test mode selection pin from right to left. A test data input pin, a test data output pin, and an empty pin; wherein, the test clock pins are electrically connected to the upper row of test clock pins and the lower row of test clock pins, The test mode selection pins are electrically connected to the upper row of test mode selection pins and the lower row of test mode selection pins, and the test data input pins are respectively connected to the upper row of test data. Material input pins and the lower row of test data input pins are electrically connected, and the test data output pins are electrically connected to the upper row of test data output pins and the lower row of test data output pins. The grounding pins are respectively electrically connected to the upper row of grounding pins and the lower row of grounding pins. The JTAG transfer circuit board as described in claim 1, wherein the upper row of pin groups has twelve pins, and the pin order of the upper row of pin groups is configured from right to left, and the upper row of The test data input pin, the test data output pin of the upper row, the test clock pin of the upper row, and the test mode selection pin of the upper row are respectively the sixth pin and the first pin of the upper row of pin groups. The seven pins, the second pin and the eleventh pin, and the other pins in the upper pin group are all ground pins in the upper row. The JTAG transfer circuit board as described in claim 1, wherein the lower row of pin groups has twelve pins, and the order of the lower row of pin groups is configured from left to right, and the lower row of The test data input pin, the test data output pin in the lower row, the test clock pin in the lower row, and the test mode selection pin in the lower row are respectively the sixth pin and the second pin of the lower pin group. The seven pins, the second pin and the eleventh pin, and the rest of the lower pin group are the lower ground pins. The JTAG transfer circuit board as described in request item 1, wherein the JTAG transfer circuit board further has a group of positioning grooves at a left and right relative position, and the positioning grooves provide the JTAG transfer circuit board and detection The fixed positioning and fool-proof of the detection platform of the machine. The JTAG transfer circuit board according to claim 1, wherein the joint test working group socket is made of polymer material, and the buckle fixing part has a geometric shape. The JTAG transfer circuit board as described in request item 1, wherein the C-type universal serial bus slot provides and detects a dual in-line memory module (Dual In-line Memory Module, DIMM) slot fixture For electrical connection. The JTAG transfer circuit board as described in claim 1, wherein the joint test working group slot provides an electrical connection with a test access port (Test Access Port, TAP) of the test access controller.

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