CN116184179A - JTAG switching circuit board - Google Patents

JTAG switching circuit board Download PDF

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Publication number
CN116184179A
CN116184179A CN202111428803.3A CN202111428803A CN116184179A CN 116184179 A CN116184179 A CN 116184179A CN 202111428803 A CN202111428803 A CN 202111428803A CN 116184179 A CN116184179 A CN 116184179A
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CN
China
Prior art keywords
pin
pins
test
row
test data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202111428803.3A
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Chinese (zh)
Inventor
赵晋东
谢新颖
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Inventec Pudong Technology Corp
Inventec Corp
Original Assignee
Inventec Pudong Technology Corp
Inventec Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Inventec Pudong Technology Corp, Inventec Corp filed Critical Inventec Pudong Technology Corp
Priority to CN202111428803.3A priority Critical patent/CN116184179A/en
Publication of CN116184179A publication Critical patent/CN116184179A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/04—Housings; Supporting members; Arrangements of terminals
    • G01R1/0408—Test fixtures or contact fields; Connectors or connecting adaptors; Test clips; Test sockets
    • G01R1/0425—Test clips, e.g. for IC's
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)

Abstract

A JTAG switching circuit board is provided with a foolproof mechanism in a joint test working group slot so as to provide the position fixing of each signal pin in the joint test working group slot, and definition verification of the signal pins can be omitted when the conversion of a connection interface is realized so as to improve the signal transmission efficiency, thereby achieving the technical effect of improving the signal transmission efficiency of the joint test working group interface conversion.

Description

JTAG switching circuit board
Technical Field
A transfer circuit board, especially a JTAG transfer circuit board which can omit the definition and verification of signal pins to improve the signal transmission efficiency when the joint test working group interface is converted.
Background
The conventional connection interface switching circuit board provides conversion of different connection interfaces, when the conversion of different connection interfaces is performed through the connection interface switching circuit board, verification of signal pin definition is required because of different connection interfaces with respect to different pin definition, and verification of signal pin definition can affect field connection efficiency.
In summary, it can be seen that the conventional conversion circuit board has a problem that the signal pin definition verification is required to affect the field connection efficiency and the signal transmission efficiency is also affected by the fact that the original connection interface has no matching circuit, so that an improved technical means is required to solve the problem.
Disclosure of Invention
In view of the problems that the existing conversion circuit board affects the field connection efficiency due to the need of signal pin definition verification and the signal transmission efficiency is affected by the fact that the original connection interface has no matching circuit, the invention discloses a JTAG switching circuit board, wherein:
the invention discloses a JTAG switching circuit board, which comprises: JTAG switch circuit boards having a Type C universal serial bus (Universal Serial Bus, USB Type-C) slot and a Joint test effort group (Joint Test Action Group, JTAG) slot.
The general serial bus slot of the type C of JTAG switching circuit board includes an upper row of pins and a lower row of pins, wherein the upper row of pins is provided with an upper row of Test Data In (TDI) pins, an upper row of Test Data Out (TDO) pins, an upper row of Test Clock (TCK) pins, an upper row of Test Mode Select (TMS) pins, a plurality of upper row of Ground (GND) pins, and the lower row of pins is provided with a lower row of Test Data input pins, a lower row of Test Data output pins, a lower row of Test Clock pins, a lower row of Test Mode Select pins and a plurality of lower row of Ground pins.
The joint test working group (Joint Test Action Group, JTAG) slot of JTAG switching circuit board, joint test working group slot have buckle fixed part, fool-proof empty slot and ten pins of left and right sides, the pin presents two rows from top to bottom and each row has five pins, test clock pin, test mode select pin, test data input pin, test data output pin and ground pin in the pin are fixed pin positions.
The test clock pins are respectively electrically connected with the upper row of test clock pins and the lower row of test clock pins, the test mode selection pins are respectively electrically connected with the upper row of test mode selection pins and the lower row of test mode selection pins, the test data input pins are respectively electrically connected with the upper row of test data input pins and the lower row of test data input pins, and the test data output pins are respectively electrically connected with the upper row of test data output pins and the lower row of test data output pins, and the ground pins are respectively electrically connected with the upper row of ground pins and the lower row of ground pins.
The circuit board disclosed by the invention is different from the prior art in that the foolproof mechanism is designed in the joint test work group slot so as to fix the positions of all signal pins in the joint test work group slot, and definition verification of the signal pins can be omitted when the joint test work group interface conversion is realized, so that the signal transmission efficiency is improved.
Through the technical means, the invention can achieve the technical effect of improving the transmission efficiency of the interface conversion signal of the joint test working group.
Drawings
Fig. 1 shows a circuit board block diagram of the JTAG switch circuit board of the present invention.
FIG. 2 is a schematic diagram of a pin of a type C universal serial bus slot of the JTAG switching circuit board of the present invention.
FIG. 3 is a schematic diagram showing the pins of the joint test working group slot of the JTAG switching circuit board of the present invention.
Wherein, the reference numerals:
10 JTAG switching circuit board
11 C-type universal serial bus slot
111. Upper row pin group
1111. Input pin for upper row test data
1112. Upper row test data output pin
1113. Upper row test clock pin
1114. Upper row test mode selection pin
1115. Upper row grounding pin
112. Lower row of pin group
1121. Lower row test data input pin
1122. Lower row test data output pin
1123. Lower row test clock pin
1124. Lower row test mode selection pin
1125. Lower row grounding pin
12. Combined test work group slot
121. Buckle fixing part
122. Fool-proof empty slot
124. Test clock pins in pins
125. Test mode selection pin
126. Test data input pin
127. Test data output pin
128. Ground pin position
13. Positioning groove
Detailed Description
The following description will be made in detail with reference to the drawings and examples, which illustrate embodiments of the present invention, thereby fully understanding and implementing the implementation process of how the present invention may be applied to solve the technical problems and achieve the technical effects.
Referring to fig. 1, fig. 1 shows a circuit board block diagram of the JTAG switching circuit board of the present invention.
The invention discloses a JTAG switching circuit board, which comprises: JTAG-transfer circuit board 10 having a type C universal serial bus slot 11 and a joint test workgroup slot 12.
Referring to fig. 2, fig. 2 is a schematic diagram showing a pin of a C-type universal serial bus slot of the JTAG switching circuit board of the present invention.
The C-type universal serial bus slot 11 of the JTAG switching circuit board 10 includes an upper pin set 111 and a lower pin set 112, wherein the upper pin set 111 has an upper Test Data In (TDI) pin 1111, an upper Test Data Out (TDO) pin 1112, an upper Test Clock (TCK) pin 1113, an upper Test Mode Select (TMS) pin 1114, a plurality of upper Ground (GND) pins 1115, and the lower pin set 112 has a lower Test Data In pin 1121, a lower Test Data Out pin 1122, a lower Test Clock pin 1123, a lower Test Mode Select pin 1124, and a plurality of lower Ground pins 1125.
The upper row of pins 111 has twelve pins, the pins of the upper row of pins 111 are configured from right to left, the upper row of pins 1111, the upper row of pins 1112, the upper row of pins 1113, the upper row of pins 1114 are respectively the sixth pin, the seventh pin, the second pin and the eleventh pin of the upper row of pins 111, and the rest of pins of the upper row of pins 111 are the upper row of pins 1115.
The lower row of pins 112 has twelve pins, the sequence of the pins of the lower row of pins 112 is configured from left to right, the lower row of test data input pins 1121, the lower row of test data output pins 1122, the lower row of test clock pins 1123, and the lower row of test mode selection pins 1124 are respectively the sixth pin, the seventh pin, the second pin, and the eleventh pin of the lower row of pins 112, and the rest of pins of the lower row of pins 112 are the lower row of pins 1125.
Referring to fig. 1 and 3, fig. 3 is a schematic diagram showing a joint test working group socket pin of the JTAG switching circuit board of the present invention.
The joint test work group slot 12 of the JTAG switching circuit board 10 has a left and right side snap fixing part 121, a fool-proof empty slot 122, and ten pins, each of which has five pins in two upper and lower rows, and a test clock pin 124, a test mode selection pin 125, a test data input pin 126, a test data output pin 127, and a ground pin 128 among the pins are fixed pin positions.
It should be noted that the five pins of the upper row in the joint test work group slot 12 are all the ground pins 128, and the five pins of the lower row in the joint test work group slot 12 are the test clock pins 124, the test mode selection pins 125, the test data input pins 126, the test data output pins 127, and the dummy pins 129 from right to left.
The Test Access Port (TAP) of the joint Test group slot 12 and the Test Access controller is made of polymer material, the latch fixing part 121 and the fool-proof hollow 122 are provided for connecting and fixing the Test Access Port of the Test Access controller and the joint Test group slot 12, the Test Access Port of the Test Access controller is provided with a first protruding fool-proof part corresponding to the fool-proof hollow 122 and a second protruding fool-proof part corresponding to the latch fixing part 121, the latch fixing part 121 and the second protruding fool-proof part present the same geometric shape, the size of the second protruding fool-proof part is smaller than or equal to the size of the latch fixing part 121, when the Test Access Port of the Test Access controller is inserted into the joint Test group slot 12 to form an electrical connection, the latch fixing of the latch fixing part 121 and the second fool-proof part provides the latch fixing between the Test Access Port of the Test Access controller and the joint Test group slot 12, and the mutual latch fixing of the Test Access Port of the Test Access controller and the joint Test group slot 12 provides the mutual latch fixing effect between the Test Access Port of the Test Access controller and the joint Test group slot 12 through the first protruding fool-proof part 122 and the first protruding fool-proof part.
The test clock pin 124 is electrically connected to the upper and lower test clock pins 1113 and 1123, the test mode selection pin 125 is electrically connected to the upper and lower test mode selection pins 1114 and 1124, the test data input pin 126 is electrically connected to the upper and lower test data input pins 1111 and 1121, and the test data output pin 127 is electrically connected to the upper and lower test data output pins 1112 and 1122, and the ground pin 128 is electrically connected to the upper and lower ground pins 1115 and 1125, respectively.
Referring to fig. 1 again, the JTAG transferring circuit board 10 further has a set of positioning grooves 13 at left and right opposite positions, and the positioning grooves 13 provide fixed positioning and foolproof of the JTAG transferring circuit board 10 and a detection platform of the detection platform, which is made of bakelite material, metal material …, etc., which is only for illustration and not limiting the application scope of the present invention.
The type-C usb socket provides electrical connection to a Dual In-line Memory Module (DIMM) socket fixture, and the joint Test workgroup socket provides electrical connection to a Test Access Port (TAP) of the Test Access controller.
In summary, the difference between the present invention and the prior art is that the foolproof mechanism is designed in the joint test work group slot to provide the position fixing of each signal pin in the joint test work group slot, so that the definition verification of the signal pin can be omitted to improve the signal transmission efficiency when the joint test work group interface is switched.
The technical means can solve the problem that the signal transmission efficiency is affected by the fact that the signal pin definition verification is required to be carried out on the existing conversion circuit board in the prior art, and further achieve the technical effect of improving the signal transmission efficiency of the joint test working group interface conversion.
Although the embodiments of the present invention have been described above, the disclosure should not be construed as directly limiting the scope of the present invention. Those of ordinary skill in the art will recognize that the invention can be practiced with modification in form and detail without departing from the spirit and scope of the disclosure. The protection scope of the present invention is still defined by the appended claims.

Claims (8)

1. A JTAG switch circuit board, comprising:
the USB Type C socket comprises an upper row pin group and a lower row pin group, wherein the upper row pin group is provided with an upper row Test Data In (TDI) pin, an upper row Test Data Out (TDO) pin, an upper row Test Clock (TCK) pin, an upper row Test Mode Select (TMS) pin and a plurality of upper row Ground (GND) pins, and the lower row pin group is provided with a lower row Test Data input pin, a lower row Test Data output pin, a lower row Test Clock pin, a lower row Test Mode Select pin and a plurality of lower row Ground pins; a kind of electronic device with high-pressure air-conditioning system
A joint test work group (Joint Test Action Group, JTAG) slot having left and right snap-fit fixing members, a fool-proof empty slot, and ten pins, the pins having upper and lower two rows and each row having five pins, test clock pins, test mode selection pins, test data input pins, test data output pins, and a plurality of ground pins being fixed pin positions;
the test clock pin is electrically connected with the upper test clock pin and the lower test clock pin, the test mode selection pin is electrically connected with the upper test mode selection pin and the lower test mode selection pin, the test data input pin is electrically connected with the upper test data input pin and the lower test data input pin, and the test data output pin is electrically connected with the upper test data output pin and the lower test data output pin, and the ground pin is electrically connected with the upper ground pin and the lower ground pin.
2. The JTAG switch circuit board of claim 1, wherein said upper-row pin group has twelve pins, wherein the order of the pins of said upper-row pin group is configured from right to left, wherein said upper-row test data input pin, said upper-row test data output pin, said upper-row test clock pin, said upper-row test mode selection pin are respectively a sixth pin, a seventh pin, a second pin and an eleventh pin of said upper-row pin group, and wherein the remaining pins of said upper-row pin group are upper-row ground pins.
3. The JTAG switch circuit board of claim 1, wherein said lower set of pins has twelve pins, said lower set of pins is arranged left to right in order, said lower test data input pins, said lower test data output pins, said lower test clock pins, said lower test mode selection pins are respectively a sixth pin, a seventh pin, a second pin and an eleventh pin of said lower set of pins, and the remaining pins of said lower set of pins are lower ground pins.
4. The JTAG switch circuit board of claim 1, wherein the five pins of the upper row of the joint test workgroup slots are all ground pins, and the five pins of the lower row of the joint test workgroup slots are the test clock pin, the test mode selection pin, the test data input pin, the test data output pin, and a null pin, respectively, from right to left.
5. The JTAG switch circuit board of claim 1, further comprising a set of positioning grooves in a set of left and right relative positions, said positioning grooves providing a fixed positioning and foolproof of said JTAG switch circuit board and a detection platform of a detection machine.
6. The JTAG switch circuit board of claim 1, wherein said joint test workgroup socket is made of a polymer material and said snap-fit feature presents a geometry.
7. The JTAG switch circuit board of claim 1, wherein said C-type universal serial bus socket provides for electrical connection with a Dual In-line Memory Module (DIMM) socket fixture for testing.
8. The JTAG switch circuit board of claim 1, wherein said joint Test workgroup slot provides for electrical connection with a Test Access Port (TAP) of a Test Access controller.
CN202111428803.3A 2021-11-29 2021-11-29 JTAG switching circuit board Pending CN116184179A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202111428803.3A CN116184179A (en) 2021-11-29 2021-11-29 JTAG switching circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202111428803.3A CN116184179A (en) 2021-11-29 2021-11-29 JTAG switching circuit board

Publications (1)

Publication Number Publication Date
CN116184179A true CN116184179A (en) 2023-05-30

Family

ID=86447553

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202111428803.3A Pending CN116184179A (en) 2021-11-29 2021-11-29 JTAG switching circuit board

Country Status (1)

Country Link
CN (1) CN116184179A (en)

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