CN116821045B - Board card structure for testing 512DUT memory device - Google Patents
Board card structure for testing 512DUT memory device Download PDFInfo
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- CN116821045B CN116821045B CN202311083304.4A CN202311083304A CN116821045B CN 116821045 B CN116821045 B CN 116821045B CN 202311083304 A CN202311083304 A CN 202311083304A CN 116821045 B CN116821045 B CN 116821045B
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- 238000012360 testing method Methods 0.000 title claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 34
- 229920002492 poly(sulfone) Polymers 0.000 claims description 9
- 238000013461 design Methods 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 238000000034 method Methods 0.000 description 4
- 239000000523 sample Substances 0.000 description 4
- 238000012938 design process Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000013256 coordination polymer Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000012812 general test Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012806 monitoring device Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7803—System on board, i.e. computer system on one or more PCB, e.g. motherboards, daughterboards or blades
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2221—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test input/output devices or peripheral units
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Abstract
The invention discloses a board card structure for testing 512DUT memory devices, which belongs to the technical field of chip testing, and particularly comprises a signal generator and a main board which are arranged in a test head, and an interface board and a socket substrate which form Hi-Fix, wherein: the main board is used for arranging signals from different signal generators into the same block and connecting the same block to the interface board, and selecting corresponding signal generator configuration according to the chip to be tested; the interface board is used as a connector to communicate the main board and the socket substrate, signals in the interface board are switched and used for placing devices which cannot be placed in the socket substrate; the socket substrate is used for directly contacting with the chip to be tested and testing different chips to be tested in the same machine and consists of a plurality of small boards; the invention reduces the complexity of the board card for chip test and increases the replaceability.
Description
Technical Field
The invention relates to the technical field of chip testing, in particular to a board card structure for testing a 512DUT memory device.
Background
With the increasing progress of electronic technology, devices such as personal computers, workstations, smart devices, monitoring devices, etc., which use various chips without exception, are becoming more important.
In the structure of the main test part of the general test apparatus (FT test), a socket is used to fix a Device under test, and when the socket is used, the socket will be mounted in a DIB (Device interface board); if a socket is not used, but is in direct contact with a device in the Handler, HIB (Handler interface board) is used. All signal generators are placed in the test head and the connectors in the signal generators will be in direct contact with either the DIB or HIB.
The integrated structure of the CP test machine is similar to that of the FT machine, and the CP test machine is in contact with a signal generator, and a PIB (Probe interface board) transmits signals of the signal generator to a Probe Card (PC) through a Probe tower, where a Probe needle in the Probe card directly contacts a die in a wafer to perform a test.
Therefore, in many cases, when testing different kinds or numbers of chips, it is necessary to replace different DIB, HIB or PIB/PC to meet the design requirement, and these interface boards require a lot of manpower and material resources in the design process, especially when facing the project of testing the chip with high complexity or number, the design difficulty and manufacturing cost of the interface boards will also increase. In addition, if problems occur in the process of later debugging or mass production of a whole interface board, the whole board can be tested and replaced, and the time and money cost of the whole project can be greatly increased.
Disclosure of Invention
The invention aims to provide a board card structure for testing a 512DUT memory device, which solves the following technical problems:
in most cases, when testing different types or numbers of chips, we need to replace different DIB, HIB or PIB/PC to meet the design requirement, and these interface boards need to spend a lot of manpower and material resources in the design process, especially when facing the project of testing high complexity or a lot of chips, the design difficulty and manufacturing cost of the interface boards will also increase; in addition, if problems occur in the process of later debugging or mass production of a whole interface board, the whole board can be tested and replaced, and the time and money cost of the whole project can be greatly increased.
The aim of the invention can be achieved by the following technical scheme:
a board card structure for 512DUT memory device testing, comprising a signal generator and a motherboard disposed within a test head, and an interface board and a socket substrate constituting a Hi-Fix, wherein:
the main board is used for arranging signals from different signal generators into the same block and connecting the same block to the interface board, and selecting corresponding signal generator configuration according to the chip to be tested;
the interface board is used as a connector to communicate the main board and the socket substrate, signals in the interface board are switched and used for placing devices which cannot be placed in the socket substrate;
the socket substrate is used for directly contacting with the DUT and testing different DUTs in the same machine and consists of a plurality of small boards.
As a further scheme of the invention: the main board comprises 4 blocks, each main board comprises 32 identical connectors, signals in different signal generators are integrated into the connectors and transmitted to the interface board, and the signals in each connector are uniformly distributed;
each interface board is provided with 4 connectors, and each main board is connected with 8 identical interface boards through cables, and is totally connected with 32 identical interface boards;
the positions of the socket base plates are the same as those of the connectors in the interface board, the socket base plates and the interface board are in one-to-one correspondence, the socket base plates comprise 32 identical socket base plates, 4 connectors are arranged in each socket base plate, and signals in each connector are distributed to 4 chips to be tested through the socket base plates for testing;
the motherboard tests 512 DUTs simultaneously in parallel.
As a further scheme of the invention: the main board comprises A, B, C and D four areas, 4 main boards correspond to the four areas according to central symmetry, each area comprises 12 columns of different SLOTs, each column of SLOTs is named as SL01, SL02, … and SL12 according to the sequence from the edge to the center of the area, each column of SLOTs corresponds to one signal generator, the signal generators are not placed in SL04, the signal generators of power types are placed in SL01 to SL03, and the signal generators of digital types and connectors connected to the interface board are placed in SL05 to SL 12.
As a further scheme of the invention: for any regional motherboard, the TOP surface and the BOTTOM surface are divided, and the TOP surface and the BOTTOM surface comprise:
PSU, the power supply board card placed on the BOTTOM surface, 3 PSU board cards are connected in each main board;
the digital board cards are placed on the BOTTOM surface, and 8 HSU board cards are connected in each main board;
HIF, a connector placed on TOP surface, 8 HIF boards connected in each motherboard, and a connector connected to the interface board by cable.
As a further scheme of the invention: and the TOP surface is provided with a main board-I, a main board-J and an interface board-ID which are used for receiving GPIO and user power signals.
As a further scheme of the invention: the wiring in each set of interface boards and HSU connectors is identical and the signals in the 3 PSUs are evenly distributed into the 8 interface board connectors.
As a further scheme of the invention: the signal distribution in each interface board connector is identical, and each interface board connector with the 2X2 layout is connected with one interface board for communicating the main board and the socket substrate.
The invention has the beneficial effects that:
(1) According to the socket substrate, the socket substrate is directly contacted with the DUT and tested, different DUTs are tested in the same machine, the DIB or the HIB is not required to be redesigned like a traditional test structure, in the conventional test structure, only one socket substrate is required to be redesigned, and as the signal distribution of each block in the main board is the same, the socket substrate is not a whole large board card, but only one small board card is required to be designed, and a plurality of boards are manufactured to be inserted in corresponding positions, so that the complexity is reduced, and the replaceability is greatly increased;
(2) The main board is a large board card, the interface board and the socket substrate are small board cards, the occupied area of the 32 interface boards or the socket substrate is smaller than that of one main board, in the traditional DIB or HIB design, the defects that the complexity of layout and wiring is improved, the thickness of a laminated layer is increased and the integrated board is not easy to replace after damage are caused by one whole oversized board card, in the designed structure, although the types of the board cards are increased, the complexity is reduced, different board cards can be designed by multiple persons in parallel, the time and money cost is greatly reduced, and in the debugging and mass production processes, the standby board card can be used for continuing to work without causing production delay.
Drawings
The invention is further described below with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of the structure of the present invention;
FIG. 2 is a schematic diagram of a test structure of the present invention;
FIG. 3 is a schematic layout of four boards of the present invention;
FIG. 4 is a schematic layout of a single motherboard region of the present invention;
fig. 5 is a schematic diagram of the wiring of the motherboard of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1-5, the present invention is a board card structure for testing 512DUT memory devices, which includes, from bottom to top, a signal generator (signal generator) disposed inside a test head, a motherboard (main board) disposed on the test head, and an interface board (interface board) and a socket substrate (socket substrate) forming a Hi-Fix, wherein the original DIB or HIB is split into three parts: motherboard, interface board and socket base plate.
The main board is mainly used for arranging signals from different signal generators into the same block and connecting the same block to the interface board, and for the same test machine and using the same signal generator configuration, the corresponding signal generator configuration is selected according to the chip to be tested, and the main board is not required to be redesigned and can be reused.
The interface board may place the device that is not placed in the socket substrate therein to save space in the socket substrate, such as some termination signals, in addition to that it is used only as a connector to communicate the motherboard with the socket substrate. We can consider whether the signals into the interface board need to be used by relay switching, and our interface board does not need to be redesigned and can be reused as long as the connector part signal allocation in the motherboard and socket substrate remains unchanged.
The socket substrate is directly contacted with the DUT (chip to be tested) and tested, and different DUTs are tested in the same machine, so that the DIB or HIB is not required to be redesigned like a traditional test structure, and only one socket substrate is required to be redesigned in the test structure of the present invention. Because the signal distribution of each block in the main board is the same, the socket substrate is not a whole large board card, but only a small board card is required to be designed, and a plurality of blocks are manufactured to be inserted in corresponding positions, so that the complexity is reduced, and the replaceability is greatly increased.
In most cases, when testing different types or numbers of chips, we need to replace different DIB, HIB or PIB/PC to meet the design requirement, and these interface boards need to spend a lot of manpower and material resources in the design process, especially when facing the project of testing high complexity or a lot of chips, the design difficulty and manufacturing cost of the interface boards will also increase; in addition, if problems occur in the later debugging or mass production process of a whole interface board, the whole board can be tested and replaced, and the time and money cost of the whole project can be greatly increased;
aiming at the two problems of the common test machine bench in the market, the structural design for testing 512 DUTs is changed, so that the problems are skillfully avoided, the complexity and the board manufacturing cost of the board card are reduced, and the replaceability of the board card is greatly improved.
Referring to fig. 2, four boards are used in the whole test process, each board has 32 identical connectors, signals from different signal generators are integrated into the connectors and transferred to the interface board, and signal distribution in each connector is identical. There are 4 connectors in each interface board, and each motherboard will be connected to 8 identical interface boards by cables, and a total of 32 identical interface boards will be used. The positions of the socket base plates and the connectors in the interface boards are identical, and each socket base plate and each interface board can be in one-to-one correspondence, so that 32 socket base plates are also used. The signals in each connector can be distributed to 4 chips to be tested in the socket substrate, and 4 connectors are arranged in each DSA, so that 512 DUTs can be tested in parallel.
From the foregoing, it will be appreciated that the motherboard is a larger board, the interface board and the socket substrate are smaller boards, and that the footprint of either the 32 interface boards or the socket substrate is smaller than that of one motherboard. In conventional DIB or HIB designs, facing testing of 512 DUTs, a monolithic oversized board card can result in drawbacks of increased complexity of layout and routing, increased stack thickness, and difficulty in replacement after damage. In the designed structure, although the types of the boards are increased, the complexity is reduced, and different boards can be designed by multiple persons in parallel, so that the time and money cost is greatly reduced. In the process of debugging and mass production, any problem can be generated by using the standby board to continue working without causing delay of production.
Referring to fig. 3, for the advantage that the interface board and the socket substrate in the design structure can be designed as a small board for clamping and use, it is first required to know that the designed test machine is divided into four areas: A. b, C and D. Corresponding to the four areas, the main board is also designed into four blocks according to central symmetry, 12 rows of different slots are divided into each block of areas, the slots sequentially increase from SL01 at the edge to SL12 in the middle, and each row of slots can be provided with a signal generator, wherein no signal generator is arranged in slot04 of the design. SL01 to SL03 place a power type signal generator, and SL05 to SL12 place a digital type signal generator and a connector connected to an interface board.
Although the motherboard is a large card, its overall structure is relatively simple, and since it is not near the DUT end, there is not much complex topology and significant small devices, all of which are all around the routing of signals from the signal generator to the connector.
Referring to fig. 4, a detailed layout of the motherboard-D area is shown, the outermost box is the edge of the board, the inner solid line box is the connector placed on TOP, and the inner dotted line box is the connector placed on BOTTOM. Each column slot corresponds to a signal generator board, and each row is distinguished according to the suffixes of a, B, C and D.
PSU: the power supply board cards are placed on the BOTTOM surface, and 3 PSU board cards are connected in each main board;
HSU: the digital board cards are placed on the BOTTOM surface, and 8 HSU board cards are connected in each main board;
HIF, a connector placed on TOP surface, 8 HIF boards connected in each motherboard, and a connector connected to the interface board by cable.
The three connectors are mainly composed in the whole main board, the rest connector main board-I, main board-J and interface board-ID are placed on the TOP surface, GPIO and user power signals are received, only auxiliary functions are achieved, and redundant description is omitted.
Referring to fig. 5, a schematic layout of any row of connectors on a motherboard is shown, each set of interface boards is identical to the layout of the HSU connectors, and signals from three PSUs are evenly distributed to eight interface board connectors. Of course, in addition to both digital and power signals being distributed to the interface board connector, there will be user power and other signals distributed evenly.
In summary, the signal distribution in each interface board connector is identical, and each 2X2 interface board connector layout is connected to an interface board card, which mainly plays a role of communicating the motherboard and the socket substrate. In addition, some terminated devices may be placed around the connector, and may be connected by relay if desired, and disconnected directly if not desired.
The foregoing describes one embodiment of the present invention in detail, but the description is only a preferred embodiment of the present invention and should not be construed as limiting the scope of the invention. All equivalent changes and modifications within the scope of the present invention are intended to be covered by the present invention.
Claims (5)
1. A board card structure for testing 512DUT memory devices, comprising a signal generator and a motherboard disposed in a test head, and an interface board and a socket substrate constituting a Hi-Fix, wherein:
the main board is used for arranging signals from different signal generators into the same block and connecting the same block to the interface board, and selecting corresponding signal generator configuration according to the chip to be tested;
the interface board is used as a connector to communicate the main board and the socket substrate, signals in the interface board are switched and used for placing devices which cannot be placed in the socket substrate;
the socket substrate is used for directly contacting with the chip to be tested and testing different chips to be tested in the same machine and consists of a plurality of small boards;
the main board comprises 4 blocks, each main board comprises 32 identical connectors, signals in different signal generators are integrated into the connectors and transmitted to the interface board, and the signals in each connector are uniformly distributed;
each interface board is provided with 4 connectors, and each main board is connected with 8 identical interface boards through cables, and is totally connected with 32 identical interface boards;
the positions of the socket base plates are the same as those of the connectors in the interface board, the socket base plates and the interface board are in one-to-one correspondence, the socket base plates comprise 32 identical socket base plates, 4 connectors are arranged in each socket base plate, and signals in each connector are distributed to 4 chips to be tested through the socket base plates for testing;
the mainboard simultaneously carries out parallel test on 512 DUTs;
the main board comprises A, B, C and D four areas, 4 main boards correspond to the four areas according to central symmetry, each area comprises 12 columns of different SLOTs, each column of SLOTs is named as SL01, SL02, … and SL12 according to the sequence from the edge to the center of the area, each column of SLOTs corresponds to one signal generator, the signal generators are not placed in SL04, the signal generators of power types are placed in SL01 to SL03, and the signal generators of digital types and connectors connected to the interface board are placed in SL05 to SL 12.
2. The board card structure for testing 512DUT memory devices according to claim 1, wherein for any area motherboard, it is divided into TOP plane and BOTTOM plane, comprising:
PSU, the power supply board card placed on the BOTTOM surface, 3 PSU board cards are connected in each main board;
the digital board cards are placed on the BOTTOM surface, and 8 HSU board cards are connected in each main board;
HIF, a connector placed on TOP surface, 8 HIF boards connected in each motherboard, and a connector connected to the interface board by cable.
3. The board card architecture for 512DUT memory device testing of claim 2 wherein the TOP surface houses a connector motherboard-I, a connector motherboard-J and a connector interface board-ID for receiving GPIO and user power signals.
4. The board card architecture for 512DUT memory device testing of claim 2 wherein the wiring in each set of interface boards and HSU connectors is identical and the signals in the 3 PSUs are evenly distributed into the 8 interface board connectors.
5. The board card architecture for testing 512DUT memory devices of claim 1 wherein the signal distribution in each interface board connector is identical, each 2X2 layout interface board connector being connected to one interface board for communicating the motherboard with the socket substrate.
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| CN202311083304.4A CN116821045B (en) | 2023-08-28 | 2023-08-28 | Board card structure for testing 512DUT memory device |
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| CN117316261B (en) * | 2023-11-28 | 2024-02-09 | 悦芯科技股份有限公司 | Specific adapting device for memory FT test |
| CN117555738B (en) * | 2024-01-09 | 2024-04-05 | 悦芯科技股份有限公司 | DPS power supply board for memory FT test |
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