KR200175408Y1 - Wafer test substrate - Google Patents

Wafer test substrate Download PDF

Info

Publication number
KR200175408Y1
KR200175408Y1 KR2019960060036U KR19960060036U KR200175408Y1 KR 200175408 Y1 KR200175408 Y1 KR 200175408Y1 KR 2019960060036 U KR2019960060036 U KR 2019960060036U KR 19960060036 U KR19960060036 U KR 19960060036U KR 200175408 Y1 KR200175408 Y1 KR 200175408Y1
Authority
KR
South Korea
Prior art keywords
probe card
execution board
wafer
input
board
Prior art date
Application number
KR2019960060036U
Other languages
Korean (ko)
Other versions
KR19980046880U (en
Inventor
함원각
김광수
Original Assignee
김영환
현대전자산업주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 김영환, 현대전자산업주식회사 filed Critical 김영환
Priority to KR2019960060036U priority Critical patent/KR200175408Y1/en
Publication of KR19980046880U publication Critical patent/KR19980046880U/en
Application granted granted Critical
Publication of KR200175408Y1 publication Critical patent/KR200175408Y1/en

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/34—Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
    • G01R1/02—General constructional details
    • G01R1/06—Measuring leads; Measuring probes
    • G01R1/067—Measuring probes
    • G01R1/073—Multiple probes
    • G01R1/07307—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
    • G01R1/07364—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch
    • G01R1/07371—Multiple probes with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card with provisions for altering position, number or connection of probe tips; Adapting to differences in pitch using an intermediate card or back card with apertures through which the probes pass
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Automation & Control Theory (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

본 고안은 실행 보드와 프로브 카드를 별도로 구성하여 그 크기를 줄임으로서 다양한 규격의 웨이퍼에 대한 테스트를 실시할 수 있는 웨이퍼 테스트용 기판을 제공한다.The present invention provides a wafer test substrate for testing wafers of various specifications by reducing the size of the execution board and the probe card separately.

본 고안은 외부의 신호가 입력되는 제1실행보드의 하부에 제1프로브 카드가 위치하되, 제1실행 보드와 제1프로브 카드는 포고 핀으로 서로 접속되며, 웨이퍼의 칩에서 발생된 신호가 입력되는 제2실행 보드의 하부에는 제2프로브 카드가 위치하되, 제2실행 보드와 제2프로브 카드는 포고 핀으로 서로 접속된다.According to the present invention, a first probe card is positioned below a first execution board to which an external signal is input, and the first execution board and the first probe card are connected to each other by pogo pins, and a signal generated from a chip of a wafer is input. A second probe card is positioned below the second execution board, and the second execution board and the second probe card are connected to each other with pogo pins.

Description

웨이퍼 테스트용 기판Wafer Test Substrate

본 고안은 웨이퍼 테스트용 기판(printed circuit board)에 관한 것으로서, 실행 보드(performance board)와 프로브 카드(probe card)를 분리, 구성함으로서 사용효율을 높일 수 있는 웨이퍼 테스트용 기판에 관한 것이다.The present invention relates to a wafer test substrate (printed circuit board), and to a wafer test substrate that can increase the use efficiency by separating and configuring the performance board (probe card) and (probe card).

웨이퍼상에 다수의 칩을 형성한 뒤, 각 칩의 성능을 테스트하는 웨이퍼 테스트용 기판은 크게 실행 보드와 프로브 카드로 이루어진다. 실행 보드는 외부에서 입력된 신호를 프로브 카드를 통하여 웨이퍼로 전달한 후 프로브 카드를 통하여 입력된 칩의 데이터를 처리함으로서 칩의 성능을 평가하게 된다. 이러한 기능을 수행하는 웨이퍼 테스트용 기판의 구성을 제1도를 통하여 설명하면 다음과 같다.After forming a plurality of chips on the wafer, the wafer test substrate for testing the performance of each chip is largely composed of an execution board and a probe card. The execution board transfers a signal input from the outside to the wafer through the probe card and then evaluates the chip performance by processing the data of the chip input through the probe card. The configuration of a wafer test substrate for performing such a function will be described with reference to FIG. 1 as follows.

제1도는 일반적인 웨이퍼 테스트용 기판의 구성도로서, 웨이퍼 테스트용 기판은 실행 보드와 프로브 카드로 구성된 제1기판(11) 및 역시 실행 보드와 프로브 카드로 구성된 제2기판(12)으로 이루어진다. 각 기판(11 및 12)의 프로브 카드에서 연장된 각 니들(13 : needle)은 지지 핀(14)에 의해 지지된 상태에서 웨이퍼(15)의 칩에 접촉한다. 제1기판(11)의 실행 보드에 외부에서 신호(예를들어 5V)가 입력되면, 이 신호는 프로브 카드의 니들(13)을 통해서 웨이퍼(15)의 칩에 입력된다. 칩은 입력된 신호를 처리하며, 칩에서 출력된 신호는 제2기판(12)의 니들 및 프로브 카드를 통하여 실행 보드로 입력됨으로서 제2기판(12)은 입력된 신호를 통하여 칩의 정상적인 작동 여부를 판별하게 된다.1 is a block diagram of a general wafer test substrate, wherein the wafer test substrate includes a first substrate 11 composed of an execution board and a probe card, and a second substrate 12 also composed of an execution board and a probe card. Each needle 13 (needle) extending from the probe card of each of the substrates 11 and 12 contacts the chip of the wafer 15 in a state supported by the support pin 14. When a signal (for example, 5 V) is externally input to the execution board of the first substrate 11, the signal is input to the chip of the wafer 15 through the needle 13 of the probe card. The chip processes the input signal, and the signal output from the chip is input to the execution board through the needle and the probe card of the second substrate 12, so that the second substrate 12 is normally operated by the input signal. Will be determined.

그러나 이와같은 구조의 기판은 실행 보드와 프로브 카드를 하나의 기판으로 형성함으로서 그 규격이 클 수 밖에 없으며, 따라서 작은 크기의 웨이퍼에 대한 테스트를 실행하는데는 여러 가지 문제점이 발생된다.However, the substrate having such a structure has a large specification by forming the execution board and the probe card as one substrate, and thus, various problems arise in executing a test on a small wafer.

따라서 본 고안은 실행 보드와 프로브 카드를 별도로 구성하여 그 크기를 줄임으로서 다양한 규격의 웨이퍼에 대한 테스트를 실시할 수 있는 웨이퍼 테스트용 기판을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a wafer test substrate capable of testing wafers of various specifications by reducing the size of the execution board and the probe card separately.

상술한 목적을 실현하기 위한 본 고안은 외부의 신호가 입력되는 제1실행 보드의 하부에 제1프로브 카드가 위치하되, 제1실행 보드와 제1프로브 카드는 포고 핀으로 서로 접속되며, 웨이퍼의 칩에서 발생된 신호가 입력되는 제2실행 보드의 하부에는 제2프로브 카드가 위치하되, 제2실행 보드와 제2프로브 카드는 포고 핀으로 서로 접속되는 것을 그 특징으로 한다.The present invention for realizing the above object is a first probe card is located on the lower portion of the first execution board to which an external signal is input, the first execution board and the first probe card is connected to each other by a pogo pin, A second probe card is positioned below the second execution board to which the signal generated from the chip is input, and the second execution board and the second probe card are connected to each other by pogo pins.

제1도는 일반적인 웨이퍼 테스트용 기판의 구성도.1 is a block diagram of a general wafer test substrate.

제2도는 본 고안의 구성도.2 is a block diagram of the present invention.

* 도면의 주요 부분에 대한 부호의 설명* Explanation of symbols for the main parts of the drawings

21, 31 : 실행보드 22, 32 : 프로브 카드21, 31: execution board 22, 32: probe card

25, 35 : 포고 핀 15 : 웨이퍼25, 35: pogo pin 15: wafer

이하, 본 고안을 첨부한 도면을 참고하여 상세히 설명한다.Hereinafter, with reference to the accompanying drawings of the present invention will be described in detail.

제2도는 본 고안의 구성도로서, 본 고안의 가장 큰 특징은 실행 보드와 프로브 카드를 서로 분리하여 구성한 것이다. 즉, 외부의 신호가 입력되는 제1실행 보드(21)의 하부에 제1프로브 카드(22)를 위치시킨 뒤 제1실행 보드(21)와 제1프로브 카드(22)를 포고 핀(25 : pogo pin)으로 서로 접속시킨다. 또한 웨이퍼(15)의 칩에서 발생된 신호가 입력되는 제2실행 보드(31) 역시 그 하부에 위치한 제2프로브 카드(32)와 포고 핀(35)으로 서로 접속된다. 한편, 각 프로브 카드(22 및 32)에서 인출된 니들(24 및 34)은 각 프로브 카드(22 및 32)에 장착된 지지 핀(23 및 33)에 의해 지지된 상태에서 웨이퍼(15)의 칩에 접촉한다.2 is a block diagram of the present invention, the biggest feature of the present invention is to configure the execution board and the probe card separately from each other. That is, the first probe board 22 is positioned under the first execution board 21 to which an external signal is input, and then the first execution board 21 and the first probe card 22 are pogo pins 25. pogo pin). In addition, the second execution board 31 to which the signal generated from the chip of the wafer 15 is input is also connected to each other by the second probe card 32 and the pogo pin 35 located below. On the other hand, the needles 24 and 34 withdrawn from the respective probe cards 22 and 32 are supported by the support pins 23 and 33 mounted on the respective probe cards 22 and 32, and the chips of the wafer 15 To contact.

이상과 같은 본 고안을 이용한 웨이퍼의 테스트 과정은 다음과 같다.The test process of the wafer using the present invention as described above is as follows.

제1실행 보드(31)에 외부에서 신호(예를들어 5V)가 입력되면, 이 신호는 포고 핀(25)을 통하여 제1프로브 카드(22)로 입력되며, 이 신호는 제1프로브 카드(22)에 접속된 니들(24)을 통해서 웨이퍼(15)의 칩에 입력된다. 칩은 입력된 신호를 처리하며, 처리된 출력은 니들(34)을 통하여 제2프로브 카드(32)로 입력된다. 제2프로브 카드(32)로 입력된 신호는 포고 핀(35)을 통하여 제2실행 보드(31)로 입력됨으로서 제2실행 보드(31)는 입력된 신호를 통하여 칩의 정상적인 작동 여부를 판별하게 된다.When a signal (for example, 5 V) is externally input to the first execution board 31, the signal is input to the first probe card 22 through the pogo pin 25, and the signal is input to the first probe card ( It is input to the chip of the wafer 15 through the needle 24 connected to 22. The chip processes the input signal, and the processed output is input to the second probe card 32 through the needle 34. The signal input to the second probe card 32 is input to the second execution board 31 through the pogo pin 35 so that the second execution board 31 determines whether the chip is normally operated through the input signal. do.

이상과 같은 본 고안은 실행 보드와 프로브 카드를 별개로 구성함과 아울러 실행 보드와 프로브 카드를 핀을 이용하여 서로 접속시킴으로서 그 크기(구성면적)가 현저하게 감소되며, 따라서 작은 규격의 웨이퍼에도 적용할 수 있어 사용효율을 향상시킬 수 있다.The present invention as described above is composed of the execution board and the probe card separately, and by connecting the execution board and the probe card to each other using pins, the size (composition area) is significantly reduced, and thus also applied to a small wafer size Can improve the efficiency of use.

Claims (1)

실행 보드와 프로브 카드로 이루어진 웨이퍼 테스트용 기판에 있어서, 외부 신호가 입력되는 제1실행 보드와, 상기 제1실행 보드 하부에 위치하며, 상기 제1실행 보드와 포그 핀에 의해 접속되는 제1프로브 카드와, 웨이퍼의 칩에서 발생된 신호가 입력되는 제2실행 보드와, 상기 제2실행 보드의 하부에 위치하되, 상기 제2실행 보드와 포고 핀에 의해 접속되며, 니들에 의해 상기 웨이퍼의 칩과 접촉되는 제2프로브 카드로 구성되는 것을 특징으로 하는 웨이퍼 테스트용 기판.A wafer test substrate comprising an execution board and a probe card, comprising: a first execution board to which an external signal is input, and a first probe positioned below the first execution board and connected to the first execution board by a fog pin; A card, a second execution board into which a signal generated from a chip of a wafer is input, and a second execution board, which is located below the second execution board, is connected by the second execution board and a pogo pin, and a needle of the wafer by a needle And a second probe card in contact with the wafer.
KR2019960060036U 1996-12-28 1996-12-28 Wafer test substrate KR200175408Y1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR2019960060036U KR200175408Y1 (en) 1996-12-28 1996-12-28 Wafer test substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR2019960060036U KR200175408Y1 (en) 1996-12-28 1996-12-28 Wafer test substrate

Publications (2)

Publication Number Publication Date
KR19980046880U KR19980046880U (en) 1998-09-25
KR200175408Y1 true KR200175408Y1 (en) 2000-05-01

Family

ID=19484805

Family Applications (1)

Application Number Title Priority Date Filing Date
KR2019960060036U KR200175408Y1 (en) 1996-12-28 1996-12-28 Wafer test substrate

Country Status (1)

Country Link
KR (1) KR200175408Y1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100600046B1 (en) * 1999-12-30 2006-07-13 주식회사 하이닉스반도체 Interface kit for testing semiconductor device
KR100347765B1 (en) * 2000-10-18 2002-08-09 삼성전자 주식회사 method and apparatus for inspecting a electric property in a wafer
AU766996B2 (en) * 2000-10-20 2003-10-30 Samsung Electronics Co., Ltd. Apparatus and method for determining a data rate of packet data in a mobile communication system
KR100592214B1 (en) * 2005-03-21 2006-06-26 주식회사 파이컴 Method for manufacturing probe card

Also Published As

Publication number Publication date
KR19980046880U (en) 1998-09-25

Similar Documents

Publication Publication Date Title
US5239191A (en) Semiconductor wafer
EP0834124B1 (en) Parallel testing of cpu cache and instruction units
WO1998053330A3 (en) Test head structure for integrated circuit tester
KR200175408Y1 (en) Wafer test substrate
EP0438127B1 (en) Semiconductor wafer
KR19990029192A (en) Semiconductor memory
JP2007188931A (en) Semiconductor device
JP3130769B2 (en) Semiconductor device
CN221103651U (en) Novel circuit board with JTAG interface
JPH0230176A (en) Semiconductor integrated circuit
JPH06232295A (en) Integrated circuit
KR200246958Y1 (en) Module Socket
JPH02141813A (en) Semiconductor device
JPS60120269A (en) Semiconductor testing apparatus
JPH0758172A (en) Universal burn-in board for test of semiconductor device
JPH06222109A (en) Integrated circuit
JPH0282547A (en) Semiconductor wafer
JPS6089955A (en) Semiconductor device
KR20000073566A (en) Method for forming monolithic wafer module in the form of array of integrated circuit chips
JP2002007164A (en) Chip for semiconductor integrated circuit and emulation system
JPH04128666A (en) Semiconductor integrated circuit
KR100483747B1 (en) Semiconductor testing system
JPH03154883A (en) Testing jig for semiconductor integrated circuit
JPS604233A (en) Integrated circuit device
JPH05121501A (en) Semiconductor integrated circuit

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E701 Decision to grant or registration of patent right
REGI Registration of establishment
FPAY Annual fee payment

Payment date: 20090102

Year of fee payment: 10

LAPS Lapse due to unpaid annual fee