JPS604233A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS604233A
JPS604233A JP11217383A JP11217383A JPS604233A JP S604233 A JPS604233 A JP S604233A JP 11217383 A JP11217383 A JP 11217383A JP 11217383 A JP11217383 A JP 11217383A JP S604233 A JPS604233 A JP S604233A
Authority
JP
Japan
Prior art keywords
input
chip
test
wafer
die
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11217383A
Other languages
Japanese (ja)
Inventor
Keiji Uemori
上森　恵治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP11217383A priority Critical patent/JPS604233A/en
Publication of JPS604233A publication Critical patent/JPS604233A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

PURPOSE:To enable uniform contact of probes of a fixed card to a four-side and pad with facility by arranging input and output pads necessary for die-sorting test on one to three sides of the IC chip. CONSTITUTION:When designing IC, the input and output pads necessary for die- sorting test of the IC chip are arranged together in a position of a pad 31 of a chip 2, whereas the input and output pads not necessary for said test are arranged in a position of pads 32-34, on the wafer. Consequently, in the process of die-sorting test on the wafer, estimate of the performance can be done only by bringing probes 5 of a fixed card 4 in contact with only the input and output pad 31. Accordingly, it is made easy to bring the probes 5 in contact with the input and output pad 31 used for die-sorting test uniformly.

Description

【発明の詳細な説明】 〔発明の技術分野〕 本発明はダイソートテストを行ないやすくした集積回路
装５ｉ１に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an integrated circuit device 5i1 that facilitates die sort testing.

〔発明の技術的背景とその問題点〕[Technical background of the invention and its problems]

一般に半導体ウェハ上で各集積回路の性能をテストする
時（ダイソートテスｔｌ、第、を図のように配置歳され
た歩積回路を用い、第２図のように集積回路の四辺に配
置された入出力端子（バンド）に対し、固定カードの針
を均等に接触させて個々の集積回路の性能を判定する。Generally, when testing the performance of each integrated circuit on a semiconductor wafer (die sort test), a die sort test circuit is placed as shown in the figure. The performance of each integrated circuit is determined by evenly touching the input/output terminals (bands) with the needles of a fixed card.

図中１はウェハ、２は集積回路チップ領域、３は人出力
パッドである。チップ２内に示されるＰの字はチップの
方向を示す。また入出力パッド３内には、ダイソートテ
ストに必・川なバンドとそうでないパッドとが混在して
いる。In the figure, 1 is a wafer, 2 is an integrated circuit chip area, and 3 is a human output pad. The letter P shown inside the chip 2 indicates the direction of the chip. Furthermore, within the input/output pad 3, there are bands that are necessary for die sort testing and pads that are not necessary.

ところで１枚のウェハ上に配？イされた集積回路チップ
の四辺に配置（ｄされた入出力パッド３に対しては、夕
′イソ−トチストに際し固定カード４の検食針５全各々
の入出力パッド３に均等に接触させる必装があるが、ウ
ェハの反シやイ士々な変形が障害となり、ウェハ上の入
出力パッドと固定カードの針をチップの四辺とも均、畔
に接触させるために、膨大な時間が費される間ｈ・自が
あった。By the way, is it distributed on one wafer? The test needles 5 of the fixed card 4 must be placed on the four sides of the integrated circuit chip (for the input/output pads 3 shown in FIG. However, various deformations of the wafer are an obstacle, and a huge amount of time is spent trying to bring the input/output pads on the wafer and the pins of the fixed card into even contact with the edge of the chip on all four sides. While I was there, I was there.

〔発明−の目的〕[Object of the invention]

本発明は上記実情に鑑みてなされたもので、ウェハ上の
チップのグイソートテスト作業ｉ］Ｆ″、率の改善がは
かれる集積回路装置をルー供し７ようとするものである
。The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide an integrated circuit device which can improve the rate of testing of chips on a wafer.

〔発明の概−゛戻〕[Summary of the invention - Return]

本発明はウェハ上での集積回路のダイソートテストに必
要な入出力パッドを一定して、それらを集積回路チップ
の一辺もしくは二辺もしくは三辺に配［ぺし、グイソー
トテスト′に必要でない入出力バンドを残りの辺に配置
することによシ、ダイソートテストに必要な入出力パッ
ドの配置辺数を減らし、以って少ない辺数だから稜辺の
パッドに固ボカードの針を容易に均寺に接触させること
ができ、グイソートテスト作業能率の改善がはかれるよ
うにしたものである。The present invention fixes the input/output pads necessary for the die sort test of integrated circuits on a wafer and arranges them on one side, two sides, or three sides of the integrated circuit chip. By placing the input/output bands on the remaining sides, the number of input/output pads required for die sort testing is reduced, and the small number of sides makes it easier to attach the hard board needle to the edge pad. It was designed to allow contact with Kyunji and improve the efficiency of the Gisoto test work.

〔発明の実／／ｌＩｉ例〕[Fruit of invention//lIi example]

以下図（酌を客照して本発明の一実施例を説明する。第
３１求１−同実施例を示すもので、これはウェハ上の一
つの隼債回１トヘチップのみを示したものである。即ち
集積回路設計の際、ウエノ）上にてその６４　ｒ？＋回
路チップのグイソートテストに必要とする入出力パッド
をチップ２のノ（ラド３１の位置に集合１配置させ、そ
の他のグイソートテストに必要でない入出力パッドをパ
ッド３２〜３４の位置に配貨するものである。An embodiment of the present invention will be explained with reference to the figure below. This figure shows only one Hayabusa chip on a wafer. In other words, when designing an integrated circuit, the 64 r? +The input/output pads required for the circuit chip test are arranged in a group at the position of the pad 31 on the chip 2, and the other input/output pads not required for the test are arranged at the positions of pads 32 to 34. It is something to be paid.

ウェハ上におけるダイソートテスト工程では、第４図の
如くチップ２の一辺の入出力パッド３１にのみ固定カー
ド４の針５を当てて性卵を詳価すればよく、固定カード
４の針５をグイソートテスト（１」の入出力パッド３１
Ｋｇ易に均等に接触させることができるものである。In the die sorting test process on the wafer, as shown in FIG. Input/output pad 31 of Guiso test (1)
Kg can be easily and evenly contacted.

なお本発明は上記実施例に１）艮られることなくζ重々
の応用が可能である。例えば実施例では集植回路チップ
の一辺にある入出力バンドで上記チップの性能判定ｊＯ
行なったが、チップの二辺捷たは三辺のみに配置された
入出力パッドで性能判定を行なうようにしてもよい。Note that the present invention can be applied in many ways without being limited to the above-mentioned embodiments. For example, in the embodiment, the performance of the above chip is determined by the input/output band on one side of the integrated circuit chip.
However, the performance may be determined using input/output pads arranged on only two or three sides of the chip.

〔発明の効果〕〔Effect of the invention〕

以上説明した如く本発明によれｌ・−よ、ウェハ上にお
ｈｆる性能評１ｉ１１ｉにおいて従来のようにチップの
四辺に配［斤された入出力パッドに固定カードの針を均
等に接触させるための調整に膨大な時間を費やすことな
く、ウェハ上でのダ・ｆソートテスト工程における作業
能率を大幅に向−ヒさせることができる。またウェハの
反りやあらゆる変形にも影・跨されることなく、ウェハ
上でのテスト工程をスムースにかつ容易に実行でき、ま
た現在実行されている製造工程を何ら変−することな〈
実施することもできるものである。As explained above, according to the present invention, in order to uniformly contact the pins of the fixed card with the input/output pads arranged on the four sides of the chip as in the conventional case during performance evaluation on a wafer. It is possible to greatly improve work efficiency in the da f sort test process on wafers without spending a huge amount of time on adjustment. In addition, the test process on the wafer can be performed smoothly and easily without being affected by wafer warpage or any deformation, and without making any changes to the currently executed manufacturing process.
It can also be implemented.

【図面の簡単な説明】[Brief explanation of drawings]

第１１メ１はウエノ・平面図、第２図は従来のダイソー
トテスト状態を示す平面図、第３図は本発明の−：ｉ、
’、　／Ａ１１例のザ郡を示す平面図、第４図は同実施
例のダイソートテスト状態を示す平面図である。 １・・・ウェハ、２・・・チップ、３．・・・ダ・ｆソ
ーテスト代ｉ係する入出力パッド、３．〜３４・・・グ
イソートテストに１列係しない入出力パッド、４・・・
固定カード、５・・・検査用針。No. 11 is a plan view of Ueno, FIG. 2 is a plan view showing a conventional die sort test state, and FIG. 3 is a plan view of the present invention.
4 is a plan view showing the die sorting test state of the same example. 1... Wafer, 2... Chip, 3. . . . input/output pads for testing, 3. ~34... Input/output pad not related to one row of guiso test, 4...
Fixed card, 5... test needle.

Claims (1)

【特許請求の範囲】[Claims] 半導体ウェハ上に配置４された集積回路チップの一辺も
しくは二辺もしくは三辺のみに沿ってダイソートテスト
用入出力パッドを具備することを特徴とする集積回路装
置。An integrated circuit device comprising die sort test input/output pads along only one, two or three sides of an integrated circuit chip arranged on a semiconductor wafer.
JP11217383A 1983-06-22 1983-06-22 Integrated circuit device Pending JPS604233A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11217383A JPS604233A (en) 1983-06-22 1983-06-22 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11217383A JPS604233A (en) 1983-06-22 1983-06-22 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS604233A true JPS604233A (en) 1985-01-10

Family

ID=14580074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11217383A Pending JPS604233A (en) 1983-06-22 1983-06-22 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS604233A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6449740B1 (en) 1998-08-05 2002-09-10 Nec Corporation Conductive paths controllably coupling pad groups arranged along one edge to CPU and to EEPROM in test mode

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