JPS6076135A - Semiconductor wafer - Google Patents

Abstract

PURPOSE:To enable to inspect the characteristics of a semiconductor wafer without decreasing the number of pieces of plural integrated circuit chips, each having a prescribed logical circuit, among the chips by a method wherein the integrated circuit chips for semiconductor wafer characteristic inspection are disposed outside of the effective area of the semiconductor wafer. CONSTITUTION:In a semiconductor wafer 11, integrated circuit chips 13, each having been formed in a complete shape and having a prescribed logical circuit, have been arranged on the whole surface of the wafer 11 in a semiconductor wafer effective area 12. Outside of the effective area 12 have been arranged integrated circuit chips 14a, 14b, 14c and 14d for semiconductor wafer characteristic inspection. According to such a way, it is possible that the integrated circuit chips for semiconductor wafer characteristic inspection are inspected at all the positions of the 14a-14d and it becomes possible that plural integrated circuit chips 13, each having a prescribed logical circuit, are disposed at all positions in the effective area of the semiconductor wafer 11.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a semiconductor wafer having a plurality of integrated circuit chips, and particularly to a semiconductor wafer having a high speed s+% integration degree and a large chip size LSI chip. Regarding.

(2) Description of Prior Art Conventionally, as shown in FIG. 1, this type of semiconductor wafer consists of a semiconductor wafer, 1 an integrated circuit chip for testing semiconductor wafer characteristics, and 4 a semiconductor wafer effective area 2. It is placed inside.

Therefore, the number of integrated circuit chips 3 having logic circuits that are actually required is smaller than the number of integrated circuit chips for semiconductor wafer characteristic testing, resulting in a disadvantage in that the yield is reduced.

(3) Detailed Description of the Invention The present invention reduces the number of integrated circuit chips having a predetermined logic circuit required by arranging integrated circuit chips for semiconductor wafer characteristic testing outside the effective area of the semiconductor wafer. It is an object of the present invention to provide a semiconductor wafer whose characteristics can be inspected.

(4) Structure of the Invention The present invention is characterized in that, in a semiconductor wafer having a plurality of integrated circuit chips, an integrated circuit chip for testing characteristics of the semiconductor wafer is provided outside the effective area of the semiconductor wafer consisting of the plurality of integrated circuit chips. It is a semiconductor wafer.

(5) Description of examples Next, embodiments of the present invention will be described with reference to the drawings.

Referring to FIG. 2, in the semiconductor wafer head 11, within the semiconductor wafer effective area 12, a complete integrated circuit chip 13 having a predetermined logic circuit is disposed over the entire surface. Further, outside the semiconductor wafer effective area, a semiconductor wafer characteristic testing integrated circuit chip 14a,
14b, 14c.

14d is arranged. In addition, this integrated circuit chip for semiconductor wafer characteristic testing has the configuration shown in FIG. It can be used to test the characteristics of semiconductor wafers. Therefore, the integrated circuit chip for semiconductor wafer characteristic testing is 14 in Figure 2.
Inspection is possible at all positions a, 14b, 14c*14ci.

By arranging the integrated circuit chips 14axd for semiconductor wafer characteristic testing outside the effective area of the semi-integrated wafer 12 in this manner, a plurality of integrated circuit chips 13 having predetermined logic circuits can be allotted within the effective area of the semiconductor wafer. It can be placed in the position of

(6) Detailed Description of the Invention As explained above, the present invention provides an effective integrated circuit chip having a predetermined logic circuit by arranging an integrated circuit chip for semiconductor wafer characteristic testing outside the effective area of a semiconductor wafer. There is no need to reduce the number of pieces, which has the effect of improving yield.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a configuration diagram according to the prior art. FIG. 2 is a plan view showing the configuration according to an embodiment of the present invention, and FIG. 3 is a diagram showing the configuration of the integrated circuit chip for inspecting semiconductor wafer characteristics shown in FIG. 2. In the figure, 1.11...semiconductor wafer, 2.12... semiconductor wafer effective area, 3
．． 13...Integrated circuit chip, 4.14a, 14
b, 14c. 14d...Integrated circuit chip for semiconductor wafer characteristic inspection %21...Internal configuration diagram of integrated circuit chip for semiconductor wafer characteristic inspection, 22a Old left terminal, 2
2b...Right side singer, 23a...Left side circuit for semiconductor wafer characteristic inspection, 23b...Right side circuit for semiconductor wafer characteristic inspection. 81 ward '382 3 arrows

Claims (1)

[Claims] A semiconductor wafer having a plurality of identical integrated circuit chips, characterized in that it has an integrated circuit chip for semiconductor wafer characteristic inspection outside an effective area including the plurality of integrated circuit chips.