JPS59117215A - Semiconductor wafer - Google Patents

Semiconductor wafer

Info

Publication number
JPS59117215A
JPS59117215A JP57226298A JP22629882A JPS59117215A JP S59117215 A JPS59117215 A JP S59117215A JP 57226298 A JP57226298 A JP 57226298A JP 22629882 A JP22629882 A JP 22629882A JP S59117215 A JPS59117215 A JP S59117215A
Authority
JP
Japan
Prior art keywords
chips
wafer
element chips
central part
vertical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57226298A
Other languages
Japanese (ja)
Inventor
Masanori Iwagami
岩上　正則
Ichiro Anjo
安生　一郎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP57226298A priority Critical patent/JPS59117215A/en
Publication of JPS59117215A publication Critical patent/JPS59117215A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/70—Microphotolithographic exposure; Apparatus therefor
    • G03F7/70425—Imaging strategies, e.g. for increasing throughput or resolution, printing product fields larger than the image field or compensating lithography- or non-lithography errors, e.g. proximity correction, mix-and-match, stitching or double patterning
    • G03F7/70433—Layout for increasing efficiency or for compensating imaging errors, e.g. layout of exposure fields for reducing focus errors; Use of mask features for increasing efficiency or for compensating imaging errors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To contrive to enhance manufacturing yield of chips at the circumferential part of a wafer by a method wherein lengths of the sides at least on one side out of sizes in length and width of the element chips to be arranged and to be formed on the circumferential part of the wafer are formed smaller than the size of element chips at the central part. CONSTITUTION:Element chips 3 are formed in a meausre type on the surface of a wafer 1, the element chips 3A of comparatively large sizes in length and width are formed at the central part 4 of the wafer surrounded with cutting lines l1, l2 in length and width, and the element chips 3B, 3C of small size are formed at the circumferential part 5 of the wafer on the outside thereof. Namely, the element chips 3A are formed by forming respective cutting lines l3, l4 in length and width at the central part 4 at the interval t1 to correspond to the element chips 3A, while the interval t2 of respective cutting lines l5, l6 in length and width to cross respectively the respective cutting lines l3, l4 are formed smaller than the interval t1 at the circumferential part 5. Accordingly, because the element chips 3B, 3C formed at the circumferential part 5 of the wafer 1 are smaller than the chips 3A at the central part 4, the number of generation of inferior chips is reduced less than the case when chips of the same size with the central part are formed even in the condition having defect density at the circumferential part of the wafer higher than the central part.

Description

【発明の詳細な説明】 本発明は半導体素子チップの製造歩留りの高い半導体ウ
ェーハに関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor wafer with a high production yield of semiconductor element chips.

ＴＲ，ＩＣ，ＬＳＩ等の半導体装置の半導体素子チップ
は、通常円板状の半導体ウエーノ・に各素子チップな桝
目状に配列形成し、これをダイシング等の手段によって
各素子チップに切断分離して形成している。そしてこの
場合一枚の半導体ウェーハには一種類の素子チップのみ
ならず複数種類の素子チップを同時に形成することも行
なわれているが、各素子チップは寸法が全て等しいもの
を形成している。Semiconductor element chips for semiconductor devices such as TRs, ICs, and LSIs are usually arranged in a grid pattern on a disk-shaped semiconductor wafer, and then cut and separated into individual element chips by means such as dicing. is forming. In this case, not only one type of element chip but also a plurality of types of element chips are simultaneously formed on one semiconductor wafer, but each element chip is formed to have the same dimensions.

ところで、この円形ウェーハを使用する半導体装置の製
造工程においては、ウェーハ表面へのホトレジスト塗布
をウェーハをスピンナにて回転させながら行なっており
、このためウェーハ中心部に対して周辺部の塗布厚が犬
となって後工程のホトリソグラフィ工程において発生す
る欠陥が周辺部はど高密度になることが知られている。By the way, in the manufacturing process of semiconductor devices using circular wafers, photoresist is applied to the wafer surface while rotating the wafer with a spinner, and as a result, the coating thickness at the periphery is slightly different from that at the center of the wafer. It is known that defects generated in the subsequent photolithography process tend to have a high density in the periphery.

また、他の工程により発生される欠陥も概ね中心部より
も周辺部においてその密度が高いものになっている。Furthermore, the density of defects generated by other processes is generally higher in the periphery than in the center.

したがって、欠陥密度の異なるウェーハの中心部から周
辺部にわたって同一寸法の素子チップな桝目状に配列し
てなる従来のウェーハでは中心部よりも周辺部において
欠陥チップが発生し易くなるのは当然であり、これＫよ
り周辺部における素子チップの製造歩留りが低下される
という不具合が生じている。Therefore, in conventional wafers in which element chips of the same size are arranged in a grid pattern from the center to the periphery of the wafer with different defect densities, it is natural that defective chips are more likely to occur in the periphery than in the center. , a problem arises in that the manufacturing yield of element chips in the peripheral region is lower than K.

したがって本発明の目的は、特にウェーハ周辺部におけ
る素子チップの製造歩留りな向上し、これによりウェー
ハ全体の歩留りを向上することができる半導体ウェーハ
を提供することにある。Accordingly, an object of the present invention is to provide a semiconductor wafer that can improve the manufacturing yield of element chips, particularly in the periphery of the wafer, and thereby improve the yield of the entire wafer.

この目的を達成するために本発明は、ウェーハの周辺部
には中心部よりも縦、横寸法の少なくとも一方の寸法が
小さな素子ペレントナ配列形成するようにしたものであ
る。In order to achieve this object, the present invention forms an array of elements in the periphery of the wafer that is smaller in at least one of the vertical and lateral dimensions than the central part.

以下、本発明を図示の実施例により説明する。Hereinafter, the present invention will be explained with reference to illustrated embodiments.

第１図は本発明の一実施例を示しており、１は一部にオ
リフラ２を有する半導体ウェーハである。FIG. 1 shows one embodiment of the present invention, and 1 is a semiconductor wafer having an orientation flat 2 in a part thereof.

このウェーハｌには表面に素子チップ（ハターン）３を
桝目状に形成しているが、縦横の切断線２Ｉ。Element chips (patterns) 3 are formed in a grid pattern on the surface of this wafer l, and the vertical and horizontal cutting lines 2I.

石、で囲まれるウェーハ中心部４には縦横寸法の比較的
大きな素子チップ３Ａを形成し、その外側のウェーハ周
辺部５にはこれよりも寸法の小さな素子チップ３Ｂを形
成している。即ち、中心部４における縦、横の各切断線
−ｅｓ　、−ｅ＜は素子チップ３Ａに見合う間隔ｔ、で
形成して素子チップ３Ａｋ形成する一方、周辺部５にお
いてはこれら各切断線−ｅ、、Ａ、に夫々交差する横、
縦の各切断線看、。Element chips 3A with comparatively large vertical and horizontal dimensions are formed in the wafer central part 4 surrounded by stones, and element chips 3B with smaller dimensions are formed in the wafer peripheral part 5 outside of this. That is, the vertical and horizontal cutting lines -es and -e< in the center part 4 are formed at intervals t corresponding to the element chip 3A to form the element chip 3Ak, while in the peripheral part 5, these cutting lines -e , , the horizontal lines that intersect A, respectively,
View each vertical cutting line.

石６の間隔ｔ、を前記間隔ｔ１よりも小さく形成してい
るのであるーしたがって、中心部４に形成した素子チッ
プ３Ａが一辺１１の正方形状として構成される一方、周
辺部５の素子チップ３Ｂは縦横辺が’１ｙ１２の長方形
状として構成されることになる。The spacing t between the stones 6 is made smaller than the spacing t1. Therefore, while the element chip 3A formed in the center part 4 is formed in a square shape with 11 sides, the element chip 3B in the peripheral part 5 is formed in a square shape. is constructed as a rectangle with vertical and horizontal sides of '1y12.

また、周辺部５の四隅に形成される素子チップ３ｃは間
隔ｔ２の縦横の切断ｍＡ’ｓ　ｔ　！６によって形成さ
れることになり、−辺がｔ、の正方形として更に小さな
チップに形成される。なお、前記各チップ３Ａ。Further, the element chips 3c formed at the four corners of the peripheral portion 5 are cut mA's t! in the vertical and horizontal directions at intervals t2. 6, and is formed into an even smaller chip as a square with -side t. Note that each of the chips 3A mentioned above.

３Ｂ、３Ｃは寸法の違いにより異なる種類のチップとし
て構成されることは言うまでもない。It goes without saying that 3B and 3C are configured as different types of chips due to the difference in size.

以上の構成によれば、ウェーハ１の周辺部５に形成され
る素子チップ３Ｂ、３Ｃは中心部４０チツプ３Ａよりも
小さくされているので、ウェーハ周辺部における欠陥密
度が中心部よりも高い状態にあっても不良チップが生じ
る数は中心部と同一寸法のチップを形成する場合よりも
低減される。According to the above configuration, the element chips 3B and 3C formed in the peripheral part 5 of the wafer 1 are made smaller than the central part 40 chips 3A, so that the defect density in the peripheral part of the wafer is higher than in the central part. Even if there are, the number of defective chips is reduced compared to forming chips with the same dimensions as the center.

また、周辺部５のチップを小さくすることにより形成で
きるチップ数の増大を図ることもでき、前述の不良チッ
プの発生数に対して良品チップの得られる確率、即ち製
造歩留を格段に向上することができるのである。Furthermore, by reducing the size of the chips in the peripheral portion 5, it is possible to increase the number of chips that can be formed, and the probability of obtaining good chips relative to the number of defective chips described above, that is, the manufacturing yield, can be significantly improved. It is possible.

ここで、ウェーハのダイシングに際しては、ウェーハの
ピッチ送り量を変化させるだけで従来と全く同様な切断
を行なうことができる。Here, when dicing the wafer, it is possible to perform the same cutting as in the conventional method by simply changing the pitch feed amount of the wafer.

第２図には本発明の他の実施例を示す。この例ではウェ
ーハＩへの縦横切断線４．、、、ｅ、にて形成される中
心部４は前例と同様に間隔ｔ、を保持させた縦横切断線
、、ｇ、、Ａ４にて素子チップ３Ａを形成しているが、
その外側の周辺部５では縦の切断線！、のみをその間隔
ｔ２が小さくなるようにし、横の切断線−ｅ６は中心部
の切断線石。と同一の間隔ｔ、となるようにしている。FIG. 2 shows another embodiment of the invention. In this example, the vertical and horizontal cutting lines 4. The center portion 4 formed by ,,,e, forms the element chip 3A by vertical and horizontal cutting lines, ,g,,A4, which maintain the interval t, as in the previous example.
At the outer periphery 5 there is a vertical cutting line! , so that the interval t2 is small, and the horizontal cutting line -e6 is the cutting line stone in the center. The interval t is the same as that of t.

なお、周辺部一部のチップ３Ｄは中心部と同一間隔の縦
横切断線にて形成されることになる。Note that the chip 3D in a part of the peripheral portion is formed with vertical and horizontal cutting lines having the same spacing as the central portion.

したがって、このウェーハＩＡによれば、周辺部５に形
成される素子チップ３Ｂは一部（図示上下部）を除いて
縦辺長を中心部の素子チップ３Ａに同一にする一方、横
辺部をこれよりも小さくした長方形として形成されるこ
とになる。換言すれは中心部のチップ３Ａに対して横辺
長を小す＜シたチップ３Ｂを周辺部に形成したことにな
る。これにより、欠陥密度の高い周辺部５に形成される
チップの小寸法化を図り、チップ不良率の低減、即ちチ
ップ製造歩留りの向上を達成することができる。Therefore, according to this wafer IA, the element chips 3B formed in the peripheral area 5 have the same vertical sides as the element chips 3A in the center except for a part (the upper and lower parts in the figure), while the horizontal sides are the same. It will be formed as a rectangle smaller than this. In other words, a chip 3B having a smaller horizontal side length than the chip 3A at the center is formed at the periphery. As a result, it is possible to reduce the size of the chip formed in the peripheral area 5 where the defect density is high, thereby achieving a reduction in the chip failure rate, that is, an improvement in the chip manufacturing yield.

ここで、前記した実施例の他に中心部と周辺部に夫々配
列する素子ペレットの形状２寸法を適宜変化させてもよ
い。但し、いずれの配列構造の場合にも周辺部のチップ
の縦横辺の少なくとも一方を中心部のチップの縦横辺の
長さよりも小さくなるように構成することが肝要である
。また、縦横の切断線はウェーハの縦横方向に連続形成
することがダイシングを容易化する上で好ましい。Here, in addition to the embodiments described above, the two dimensions of the shape of the element pellets arranged in the center and the periphery may be changed as appropriate. However, in any arrangement structure, it is important that at least one of the vertical and horizontal sides of the chips in the peripheral area is configured to be smaller than the length of the vertical and horizontal sides of the chips in the center area. Further, it is preferable to form the vertical and horizontal cutting lines continuously in the vertical and horizontal directions of the wafer in order to facilitate dicing.

以上のように本発明の半導体ウェーハによれば、ウェー
ハ周辺部に配列形成する素子チップの縦横寸法の少なく
とも一方の辺の長さな中心部の素子チップ寸法よりも小
さく形成しているので、欠陥密度の高いウェーハ周辺部
における不良チップの発生数を低減し、これにより周辺
部でのチップ製造歩留りの向上を図るのはもとよりクエ
ーノ・全体におけるチップ製造歩留りの向上を達成する
ことができるという効果を奏する。As described above, according to the semiconductor wafer of the present invention, since the element chips arranged at the periphery of the wafer are formed smaller than the length of at least one of the vertical and horizontal sides of the element chips in the center, defects This has the effect of reducing the number of defective chips in the densely populated wafer periphery, thereby improving the chip manufacturing yield in the wafer periphery, as well as improving the overall chip manufacturing yield. play.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の一実施例のウェーハ平面図、第２図は
他の実施例のウェーハ平面図である。 １、ＬＡ・・・ウェーハ、３・・・チップ、３Ａ〜３Ｄ
・・・チップ、４・・・中心部、５・・・周辺部、−ａ
ｌ　、　４　。 形、・・・縦切断線、−８；　、４、−８６・・・横切
断線、ｔＩ。 ｔ、・・・間隔。 代理人　弁理士　　薄　１）利　幸−７′１１ 一′４− 第　　１　　図 第　　２　　図FIG. 1 is a wafer plan view of one embodiment of the present invention, and FIG. 2 is a wafer plan view of another embodiment. 1, LA...wafer, 3... chip, 3A-3D
... Chip, 4 ... Center, 5 ... Periphery, -a
l, 4. Shape... Vertical cutting line, -8; , 4, -86... Horizontal cutting line, tI. t,...interval. Agent Patent Attorney Usui 1) Toshiyuki-7'11 1'4- Figure 1 Figure 2

Claims (1)

【特許請求の範囲】 １、略円形の半導体ウェーハに複数個の素子チップを桝
目状に配列形成するようにしたものにおいて、ウェーハ
の周辺部に形成する素子チップの縦横寸法の少なくとも
一方な中心部に形成する素子チップの縦横町法よりも小
さくなるように形成したことを特徴とする半導体ウェー
・・。 ２　周辺部の素子チップの縦横寸法の一方をのみ小さく
してなる特許請求の範囲第１項記載の半導体ウェーハ。 ３、周辺部の素子のチップの縦横寸法の両方を小さくし
てなる特許請求の範囲第１項記載の半導体ウェーハ。[Scope of Claims] 1. In a device in which a plurality of element chips are arranged in a grid pattern on a substantially circular semiconductor wafer, a central portion of at least one of the vertical and horizontal dimensions of the element chips formed on the periphery of the wafer; A semiconductor wafer characterized in that it is formed to be smaller than the vertical, horizontal, and vertical pattern of element chips formed in... 2. The semiconductor wafer according to claim 1, in which only one of the vertical and horizontal dimensions of the element chips in the peripheral portion is made smaller. 3. A semiconductor wafer according to claim 1, in which both vertical and horizontal dimensions of chips of peripheral elements are reduced.
JP57226298A 1982-12-24 1982-12-24 Semiconductor wafer Pending JPS59117215A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57226298A JPS59117215A (en) 1982-12-24 1982-12-24 Semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57226298A JPS59117215A (en) 1982-12-24 1982-12-24 Semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS59117215A true JPS59117215A (en) 1984-07-06

Family

ID=16843014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57226298A Pending JPS59117215A (en) 1982-12-24 1982-12-24 Semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS59117215A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0709740A1 (en) * 1994-09-30 1996-05-01 Texas Instruments Incorporated Integrated circuit and method of making the same
EP0768575A2 (en) * 1995-10-10 1997-04-16 Deutsche ITT Industries GmbH Method of optimising the arrangement of semiconductor elements on a semiconductor wafer
US9679722B2 (en) 2014-10-30 2017-06-13 Lsis Co., Ltd. Interlock apparatus of vacuum circuit breaker

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0709740A1 (en) * 1994-09-30 1996-05-01 Texas Instruments Incorporated Integrated circuit and method of making the same
EP0768575A2 (en) * 1995-10-10 1997-04-16 Deutsche ITT Industries GmbH Method of optimising the arrangement of semiconductor elements on a semiconductor wafer
EP0768575A3 (en) * 1995-10-10 1997-11-19 Deutsche ITT Industries GmbH Method of optimising the arrangement of semiconductor elements on a semiconductor wafer
US9679722B2 (en) 2014-10-30 2017-06-13 Lsis Co., Ltd. Interlock apparatus of vacuum circuit breaker

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