JP2008004772A - Semiconductor device and semiconductor wafer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor wafer that are composed by forming a transistor having a trench gate structure in a semiconductor chip, and prevent the occurrence of warpage due to a trench gate. <P>SOLUTION: The semiconductor device 100 is composed by forming the transistor having the trench gate structure in the semiconductor chip 1c. The trench gate of the transistor is composed of a plurality of linear gate elements Te formed on the surface layer of the semiconductor chip 1c. Each of gate element parallel sets Pa-Pd is composed of the linear gate elements Te arranged in parallel. A plurality of sets of the gate element parallel sets Pa-Pd are arranged on the surface layer of the semiconductor chip 1c. It is composed so as to make the line direction of the linear gate elements Te in each gate element parallel set Pa-Pd arranged adjacently to each other different from each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a semiconductor wafer in which a transistor having a trench gate structure is formed.

  Semiconductor devices in which a transistor having a trench gate structure is formed include, for example, Japanese Patent Application Laid-Open No. 11-266010 (Patent Document 1), Japanese Patent Application Laid-Open No. 2002-16252 (Patent Document 2), and Japanese Patent Application Laid-Open No. 2003-101020. (Patent Document 3).

  FIG. 7 is a schematic cross-sectional view of a semiconductor device 90 which is a conventional semiconductor device disclosed in Patent Document 3 and includes an IGBT (Insulated Gate Bipolar Transistor) having a trench gate structure. FIG. 8 is a plan view showing a typical arrangement example of the main part of the semiconductor device 90 shown in FIG. 7 with respect to the semiconductor chip 1c.

  In the semiconductor device 90, as shown in FIG. 7, the semiconductor layer 12 having a uniform thickness is formed on the surface of the semiconductor chip 1 c serving as the IGBT drift layer 11. The emitter region 13 is selectively formed in the surface layer of the semiconductor layer 12. The gate electrode 14 made of polysilicon is provided through a gate oxide film 15 inside a trench that reaches the drift layer 11 from the surface of the emitter region 13 through the semiconductor layer 12. The emitter electrode 16 is formed in common contact with the emitter region 13 and a part of the semiconductor layer 12 (a portion sandwiched between two adjacent emitter regions 13) 12 a through the interlayer insulating film 17. On the other hand, a collector layer 18 is formed on the back surface of the semiconductor chip 1c, and a collector electrode 19 is further formed.

In the semiconductor device 90, as shown in FIGS. 7 and 8, the semiconductor layer 12 is divided into a plurality of regions by a trench gate Tg composed of a gate oxide film 15 and a gate electrode 14. Of the plurality of divided regions by the trench gate Tg of the semiconductor layer 12, the divided region where the emitter electrode 16 is in contact is a fixed potential region 12a, and the divided region where the emitter electrode 16 is not in contact is a floating potential region 12b. At this time, in the semiconductor device 90, the fixed potential regions 12a and the floating potential regions 12b are alternately arranged as illustrated.
Japanese Patent Laid-Open No. 11-266010 JP 2002-16252 A JP 2003-101020 A

  FIG. 9A is a schematic plan view of a conventional semiconductor wafer 1w before cutting out the semiconductor chip 1c on which the semiconductor device 90 shown in FIG. 8 is formed. FIG. 9B is a schematic plan view of FIG. It is sectional drawing in the dashed-dotted line AA in FIG. In FIG. 9A, only the trench gate Tg of the semiconductor device 90 shown in FIGS. 7 and 8 is shown in a simplified manner. In the semiconductor wafer 1w in FIG. 9A, the semiconductor device 90 is cut out along the line indicated by the broken line, and the semiconductor chip 1c in which the semiconductor device 90 shown in FIG. 8 is formed is obtained.

  In the conventional semiconductor wafer 1w shown in FIG. 9A, the trench gates Tg of the semiconductor device 90 having a trench gate structure are arranged in one direction within the plane of the semiconductor wafer 1w. For this reason, as shown in FIG. 9B, after the trench T is formed in the semiconductor wafer 1w during the manufacturing, the semiconductor wafer 1w is likely to be warped downward. In particular, as the number of trenches T increases due to pattern miniaturization or the like, or the semiconductor wafer 1w becomes thinner (for example, 200 μm or less) for improving the characteristics of the IGBT, the semiconductor wafer 1w formed by the trench T is formed. The degree of warpage becomes large (for example, several mm to several tens of mm). For this reason, the warped semiconductor wafer 1w becomes difficult to be transferred to the subsequent process, and cracks, drops, etc. occur in the process, or the exposure becomes uneven within the wafer surface, resulting in an exposure failure. In addition, processing such as polishing and cutting cannot be performed, and the yield decreases.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device and a semiconductor wafer in which a transistor having a trench gate structure is formed, and a semiconductor device and a semiconductor wafer that are unlikely to be warped by a trench gate.

  The semiconductor device according to claim 1 is a semiconductor device in which a transistor having a trench gate structure is formed in a semiconductor chip, wherein a plurality of trench gates of the transistor are formed in a surface layer portion of the semiconductor chip. A gate element portion parallel set is configured by the line-shaped gate element portions, which are composed of line-shaped gate element portions and arranged in parallel, and a plurality of sets of the gate element portion parallel sets are arranged on the surface layer portion of the semiconductor chip. The line-shaped gate element portions of the gate element portion parallel set arranged adjacent to each other have different line directions.

  In the semiconductor device described above, the parallel gate element portions arranged adjacent to each other have different line directions. Therefore, in the semiconductor chip on which the semiconductor device is formed, there are at least two sets of gate element part parallel sets having different line directions. For this reason, when a plurality of semiconductor devices are manufactured by cutting from a single semiconductor wafer, no matter what the plurality of semiconductor devices are arranged on the semiconductor wafer, all the line gate element portions are on the semiconductor wafer. In a specific line direction.

  Accordingly, the semiconductor wafer in the process of manufacturing the semiconductor device is unlikely to warp even after the trench is formed. Therefore, the semiconductor device manufactured by cutting out from the semiconductor wafer can also be a semiconductor device in which warpage due to the trench gate hardly occurs.

  In addition, the semiconductor wafer is easily transported to a subsequent process, is not easily cracked or dropped, and is less susceptible to processing defects such as exposure failure and polishing / cutting. For this reason, the semiconductor device manufactured by cutting out from the semiconductor wafer can have a high yield and can be an inexpensive semiconductor device.

  According to a second aspect of the present invention, in the semiconductor device, it is preferable that the line-shaped gate element portions of the parallel arrangement of the gate element portions arranged adjacent to each other have a line direction substantially orthogonal to each other. . According to this, the line-shaped gate element part of the gate element part parallel set arrange | positioned adjacently will not have the component of the same line direction. Therefore, as compared to the case where the line-shaped gate element portions of the gate element portion parallel set arranged adjacent to each other cross each other obliquely, the line direction is more dispersed, and the semiconductor wafer and the semiconductor in the process of manufacturing the semiconductor device Device warpage can be further suppressed.

  In addition, as described in claim 3, it is preferable that the gate element part parallel sets arranged adjacent to each other having different line directions are arranged in a checkered pattern. This also makes it possible to finely disperse the line direction of the line-shaped gate element portion in the semiconductor device and the semiconductor wafer in the process of manufacturing the semiconductor device, and the semiconductor wafer and the semiconductor in the process of manufacturing the semiconductor device. Device warpage can be further suppressed.

  The transistor having the trench gate structure formed in the semiconductor device may be an IGBT, for example. The IGBT can improve the characteristics by reducing the thickness of the semiconductor chip. Further, by taking the arrangement of the line-shaped gate elements described above, it is possible to prevent warping even when the thickness of the semiconductor chip is reduced.

  According to another aspect of the present invention, there is provided a semiconductor device in which an IGBT having a trench gate structure is formed on a semiconductor chip, wherein the trench gate of the IGBT is formed on a surface layer portion of the semiconductor chip and is parallel to the semiconductor device. Predetermined impurity diffusion regions selectively formed in the surface layer portion of the semiconductor chip by the plurality of line-shaped gate element portions are formed in a plurality of regions. When the divided region to which the IGBT emitter electrode is connected is the first divided region and the divided region to which the IGBT emitter electrode is not connected is the second divided region among the plurality of divided regions, In the semiconductor device in which the first divided region and the second divided region are alternately arranged in the surface layer portion of the semiconductor chip, the second divided region is arranged in front of the second divided region. A plurality of parallel line-shaped dummy element portion together with the same cross-sectional structure as the trench gate may be configured to become disposed in a different line direction and the line-shaped gate element portion.

  In the semiconductor device, the line-shaped gate element portion and the line-shaped dummy element portion arranged in the second dividing region have different line directions. Therefore, in the semiconductor chip on which the semiconductor device is formed, there are a line-shaped gate element portion and a line-shaped dummy element portion having different line directions. For this reason, when a plurality of semiconductor devices are manufactured by cutting out from a single semiconductor wafer, no matter how the plurality of semiconductor devices are arranged on the semiconductor wafer, all the line gate elements and the line dummy The element portions are not aligned in a specific line direction on the semiconductor wafer.

  Accordingly, the semiconductor wafer in the process of manufacturing the semiconductor device is unlikely to warp even after the trench is formed. Therefore, the semiconductor device manufactured by cutting out from the semiconductor wafer can also be a semiconductor device in which warpage due to the trench gate hardly occurs.

  In addition, the semiconductor wafer is easily transported to a subsequent process, is not easily cracked or dropped, and is less susceptible to processing defects such as exposure failure and polishing / cutting. For this reason, the semiconductor device manufactured by cutting out from the semiconductor wafer can also be a low-cost semiconductor device with a high yield.

  According to a sixth aspect of the present invention, in the semiconductor device, the line-shaped gate element portion and the line-shaped dummy element portion preferably have line directions that are substantially orthogonal to each other. According to this, the line-shaped gate element portion and the line-shaped dummy element portion do not have the same line direction component. For this reason, compared with the case where the line-shaped gate element portion and the line-shaped dummy element portion cross each other at an angle, the line direction is more dispersed and the warpage of the semiconductor wafer and the semiconductor device in the process of manufacturing the semiconductor device is further suppressed. can do.

  According to a seventh aspect of the present invention, in the semiconductor device, the line of the line-shaped dummy element portion may have a ring shape. Also in this case, the line-shaped gate element portion and the line-shaped dummy element portion arranged in the second dividing region have mutually different line directions, and the occurrence of warpage can be suppressed.

  As described in claim 8, the thickness of the semiconductor chip may be a thickness of 300 μm or less, and can improve both characteristics when warping is prevented and an IGBT is formed. Further, it may be 150 μm or less.

  The invention described in claims 10 to 15 relates to a semiconductor wafer when a plurality of semiconductor devices are manufactured by cutting out from a single semiconductor wafer, and in particular, a plurality of line-shaped gate elements arranged in parallel. The present invention relates to a semiconductor wafer suitable for manufacturing a semiconductor device in which a trench gate composed of a portion is formed.

  The semiconductor wafer according to claim 10 is a semiconductor wafer in which a plurality of unit configuration regions of a semiconductor device are arranged, and the semiconductor device is a semiconductor device in which a transistor having a trench gate structure is formed. The trench gate of the transistor is formed in a surface layer portion of the semiconductor wafer, and is composed of a plurality of line-shaped gate element portions arranged in parallel, and the line-shaped gate element of the unit configuration region disposed adjacent to the trench gate. The parts are characterized by having different line directions.

  In the semiconductor wafer, the line-shaped gate element portions of the unit configuration regions arranged adjacent to each other have different line directions. Therefore, in the semiconductor wafer, there are at least two unit constituent regions having different line directions. For this reason, not all the line-shaped gate element parts are aligned in a specific line direction on the semiconductor wafer.

  Therefore, the semiconductor wafer can be a semiconductor wafer which hardly warps even after the trench is formed. Further, a semiconductor device manufactured by cutting out from the semiconductor wafer can also be a semiconductor device in which warpage due to a trench gate hardly occurs.

  In addition, the semiconductor wafer can be easily transported to a subsequent process, is not easily cracked or dropped, and is less prone to processing defects such as exposure failure and polishing / cutting. For this reason, a semiconductor device manufactured by cutting out from the semiconductor wafer can be a low-cost semiconductor device with a high yield.

  The semiconductor wafer according to an eleventh aspect is characterized in that the line-shaped gate element portions of the unit configuration regions arranged adjacent to each other have line directions substantially perpendicular to each other. The semiconductor wafer according to a twelfth aspect is characterized in that the unit constituent regions arranged adjacent to each other having different line directions are arranged in a checkered pattern. The semiconductor wafer according to claim 13 is characterized in that the transistor is an IGBT.

  In addition, the effect obtained by the semiconductor wafer of the said Claims 11-13 is the same as the effect demonstrated in the semiconductor device of Claims 2-4, The description is abbreviate | omitted.

  Further, as in the semiconductor chip of the semiconductor device according to the eighth and ninth aspects, the thickness of the semiconductor wafer can improve both the prevention of warpage and the improvement of the characteristics when the IGBT is formed. The thickness may be 300 μm or less, and particularly may be 150 μm or less as described in claim 15.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a schematic plan view of a semiconductor device 100 as an example of the semiconductor device of the present invention.

  A semiconductor device 100 shown in FIG. 1 is a semiconductor device in which a transistor having a trench gate structure is formed on a semiconductor chip 1c. The transistor having a trench gate structure formed in the semiconductor device 100 can be, for example, an IGBT (Insulated Gate Bipolar Transistor) as shown in FIG. For simplification, in FIG. 1, only the trench gate of the semiconductor device 100 formed in the semiconductor chip 1c is shown by a bold line. Although the sectional structure of the semiconductor device 100 is not shown, the trench gate structure formed in the semiconductor device 100 can be the same as the trench gate structure in the conventional semiconductor device 90 shown in FIG. That is, as shown in FIG. 7, a trench gate structure is formed by embedding a gate electrode 14 made of polysilicon through a gate oxide film 15 in the trench T.

  In the semiconductor device 100 of FIG. 1, the trench gate of the transistor is composed of a plurality of line-shaped gate element portions Te formed in the surface layer portion of the semiconductor chip 1c, and the line-shaped gate element portions Te arranged side by side in parallel. The gate element part parallel group Pa-Pd enclosed with the dashed-dotted line in the figure is comprised. In the semiconductor device 100, the four gate element part parallel sets Pa to Pd are arranged on the surface layer part of the semiconductor chip 1c, and the gate element part parallel sets Pa to Pd arranged adjacent to each other include the line-shaped gate element parts Te of the gate element part parallel sets Pa to Pd. The arrangement has different line directions.

  As described above, in the semiconductor device 100 of FIG. 1, the line-shaped gate element portions Te of the gate element portion parallel sets Pa to Pd arranged adjacent to each other have different line directions. Therefore, in the semiconductor chip 1c on which the semiconductor device 100 is formed, there are at least two sets of gate element part parallel sets having different line directions (Pa, Pd and Pb, Pc). Therefore, for example, when a plurality of semiconductor devices 100 shown in FIG. 1 are manufactured by cutting out from one semiconductor wafer as shown in FIG. 9A, how the plurality of semiconductor devices 100 are arranged on the semiconductor wafer. However, not all the line-shaped gate element portions Te are aligned in a specific line direction on the semiconductor wafer.

  Therefore, the semiconductor wafer in the process of manufacturing the semiconductor device 100 is unlikely to warp even after the trench is formed. For this reason, the semiconductor device 100 manufactured by cutting out from the semiconductor wafer is also a semiconductor device in which warpage due to the trench gate hardly occurs.

  In addition, the semiconductor wafer is easily transported to a subsequent process, is not easily cracked or dropped, and is less susceptible to processing defects such as exposure failure and polishing / cutting. For this reason, the semiconductor device 100 manufactured by cutting out from the semiconductor wafer can be a high-yield and inexpensive semiconductor device.

  In particular, in the semiconductor device 100 of FIG. 1, the gate element portions Te of the gate element portion parallel sets Pa to Pd arranged adjacent to each other have line directions that are substantially orthogonal to each other. As a result, the line-shaped gate element portions Te of the gate element portion parallel sets Pa to Pd arranged adjacent to each other do not have components in the same line direction. Therefore, as compared with the case where the line-shaped gate element portions of the gate element portion parallel set arranged adjacent to each other cross each other obliquely (not shown), the semiconductor is in the process of manufacturing the semiconductor device 100 with the line direction more dispersed. Warpage of the wafer and the semiconductor device 100 can be further suppressed.

  Further, as in the semiconductor device 100 shown in FIG. 1, the plurality of sets of gate element unit parallel sets are formed by arranging adjacent gate element unit parallel sets having different line directions in a checkered pattern. It is preferable. This also makes it possible to more finely disperse the line direction of the line-shaped gate element portion Te in the semiconductor device and the semiconductor wafer in the process of manufacturing the semiconductor device. The warp of the semiconductor device can be further suppressed.

  As described above, the transistor having the trench gate structure formed in the semiconductor device 100 of FIG. 1 can be an IGBT, for example. The characteristics of the IGBT can be improved by reducing the thickness of the semiconductor chip 1c. Moreover, even if it is a case where the thickness of the semiconductor chip 1c is reduced by taking arrangement | positioning of the line-shaped gate element part Te mentioned above, generation | occurrence | production of curvature can be prevented.

  2 to 5 are schematic plan views of the semiconductor devices 101 to 107 as another example of the semiconductor device according to the present invention.

  Each of the semiconductor devices 101 to 107 shown in FIGS. 2 to 5 is a semiconductor device in which an IGBT having a trench gate structure is formed on the semiconductor chip 1c. 2 to 5, the same reference numerals are given to the same parts as those of the semiconductor device 90 shown in FIGS. 7 and 8. For simplification, the trench gates Tg are also indicated by thick lines in the semiconductor devices 101 to 107 of FIGS. The cross-sectional structure of the semiconductor devices 101 to 107 is similar to the cross-sectional structure of the semiconductor device 90 shown in FIG.

  Each of the semiconductor devices 101 to 107 in FIGS. 2 to 5 has a structure similar to that of the semiconductor device 90 illustrated in FIGS. 7 and 8. In other words, in the semiconductor devices 101 to 107, the semiconductor layer 12 having a uniform thickness is formed on the surface of the semiconductor chip 1c which becomes the IGBT drift layer 11 shown in FIG. The emitter region 13 is selectively formed in the surface layer of the semiconductor layer 12. The gate electrode 14 made of polysilicon is provided through a gate oxide film 15 inside a trench that reaches the drift layer 11 from the surface of the emitter region 13 through the semiconductor layer 12. The emitter electrode 16 is formed in common contact with the emitter region 13 and a part of the semiconductor layer 12 (a portion sandwiched between two adjacent emitter regions 13) 12 a through the interlayer insulating film 17. On the other hand, a collector layer 18 is formed on the back surface of the semiconductor chip 1c, and a collector electrode 19 is further formed.

  In the semiconductor devices 101 to 107 of FIGS. 2 to 5, the IGBT trench gate is formed in the surface layer portion of the semiconductor chip 1 c and is composed of a plurality of linear gate element portions Tg arranged in parallel. A predetermined impurity diffusion region 12 (corresponding to the semiconductor layer 12 shown in FIG. 7) selectively formed in the surface layer portion of the semiconductor chip 1c by the plurality of line-shaped gate element portions Tg becomes a plurality of regions 12a, 12b. It is divided into two. Of the plurality of divided regions 12a and 12b, a divided region to which the IGBT emitter electrode is connected is a first divided region 12a (corresponding to the fixed potential region 12a shown in FIG. 7), and a divided region to which the IGBT emitter electrode is not connected is formed. A second divided region 12b (corresponding to the floating potential region 12b shown in FIG. 7) is used. At this time, in the semiconductor devices 101 to 107, the first divided regions 12a and the second divided regions 12b are alternately arranged in the surface layer portion of the semiconductor chip 1c as illustrated.

  On the other hand, unlike the semiconductor device 90 shown in FIG. 8, the semiconductor devices 101 to 107 in FIGS. 2 to 5 have a plurality of mutually similar bold lines having the same cross-sectional structure as the trench gate Tg in the second dividing region 12 b. Parallel line-shaped dummy element portions Tda to Tdd are arranged in a line direction different from that of the line-shaped gate element portion Tg. The line-shaped dummy element portions Tda to Tdd are dummy trench structures that are not connected to the gate wiring of the IGBT and do not have a gate function.

  In the semiconductor devices 101 and 102 of FIGS. 2A and 2B, the line-shaped dummy element portion Tda is arranged in an oblique line direction with respect to the line-shaped gate element portion Tg. In the semiconductor device 101 of FIG. 2A, the line-shaped dummy element portions Tda are arranged in the vertical direction next to the left and right sides of the drawing, and in the semiconductor device 102 of FIG. The dummy element portions Tda are arranged so as to be shifted in the vertical direction adjacent to each other on the left and right in the drawing.

  In the semiconductor devices 101 and 102 of FIGS. 2A and 2B, the line-shaped gate element portion Tg and the line-shaped dummy element portion Tda disposed in the second dividing region 12b have different line directions. Yes. Therefore, in the semiconductor chip 1c on which the semiconductor devices 101 and 102 are formed, there are a line-shaped gate element portion Tg and a line-shaped dummy element portion Tda having different line directions. For this reason, when a plurality of semiconductor devices 101 and 102 are manufactured by cutting out from a single semiconductor wafer, all line-shaped gate elements are arranged no matter how the plurality of semiconductor devices 101 and 102 are arranged on the semiconductor wafer. The portion Tg and the line-shaped dummy element portion Tda are not aligned in a specific line direction on the semiconductor wafer.

  Accordingly, the semiconductor wafer in the process of manufacturing the semiconductor devices 101 and 102 is unlikely to warp even after the trench is formed. For this reason, the semiconductor devices 101 and 102 manufactured by cutting out from the semiconductor wafer can also be semiconductor devices in which warpage due to the trench gate hardly occurs.

  In addition, the semiconductor wafer is easily transported to a subsequent process, is not easily cracked or dropped, and is less susceptible to processing defects such as exposure failure and polishing / cutting. For this reason, the semiconductor devices 101 and 102 manufactured by cutting out from the semiconductor wafer can also be a low-cost semiconductor device with a high yield.

  In the semiconductor devices 103 and 104 of FIGS. 3A and 3B, the line-shaped dummy element portion Tdb is arranged in the line direction substantially orthogonal to the line-shaped gate element portion Tg. In the semiconductor device 103 of FIG. 3A, the line-shaped dummy element portions Tdb are arranged in the vertical direction next to the left and right of the drawing, and in the semiconductor device 104 of FIG. The dummy element portions Tdb are arranged so as to be shifted in the vertical direction adjacent to each other on the left and right in the drawing. In the semiconductor devices 103 and 104 in FIGS. 3A and 3B, the line-shaped gate element portion Tg and the line-shaped dummy element portion Tdb do not have the same line direction component. Therefore, compared with the semiconductor devices 101 and 102 of FIGS. 2A and 2B in which the line-shaped gate element portion Tg and the line-shaped dummy element portion Tda cross each other at an angle, the line direction is more dispersed, and during the manufacturing process. Warpage of a certain semiconductor wafer and the semiconductor devices 103 and 104 can be further suppressed.

  In the semiconductor device 105 of FIG. 4, the zigzag line-shaped dummy element portion Tdc is arranged in the second divided region 12b. In the semiconductor devices 106 and 107 in FIGS. 5A and 5B, the ring-shaped line-shaped dummy element portion Tdd is disposed in the second divided region 12b. Thus, the lines of the line-shaped dummy element portions Tdc and Tdd may be in a zigzag shape or a ring shape. Also in this case, the line-shaped dummy element portions Tdc and Tdd arranged in the line-shaped gate element portion Tg and the second dividing region 12b have different line directions, and the occurrence of warpage can be suppressed.

  In the semiconductor devices 100 to 107 shown in FIGS. 1 to 5, the thickness of the semiconductor chip 1c may be a thickness of 300 μm or less that can achieve both the prevention of warpage and the improvement of characteristics when an IGBT is formed. In particular, it may be 150 μm or less.

  Next, in another example of the present invention, a semiconductor wafer in which a plurality of semiconductor devices are manufactured by cutting out from one semiconductor wafer, in particular, from a plurality of line-shaped gate element portions arranged in parallel. A semiconductor wafer suitable for manufacturing a semiconductor device in which a trench gate is formed will be described.

  FIG. 6 is an example of the semiconductor wafer of the present invention, and FIG. 6A is a schematic plan view of the semiconductor wafer 1x. 6B and 6C are schematic plan views of the semiconductor devices 92 and 93, respectively, which are another example of the semiconductor device 91 formed on the semiconductor wafer 1x of FIG. 6A. In the semiconductor wafer 1x shown in FIG. 6A, the same reference numerals are given to the same parts as those of the semiconductor wafer 1w shown in FIG. Also, in the semiconductor devices 92 and 93 shown in FIGS. 6B and 6C, the same reference numerals are given to the same portions as those of the semiconductor device 90 shown in FIG.

  A semiconductor wafer 1x shown in FIG. 6A is a semiconductor wafer in which a plurality of unit configuration regions 1c of a semiconductor device 91 surrounded by a broken line in the drawing are arranged. The semiconductor device 91 formed on the semiconductor wafer 1x in FIG. 6A is a semiconductor device in which a transistor having a trench gate structure is formed. The trench gate of the transistor is formed of a plurality of line-shaped gate element portions Tg formed in the surface layer portion of the semiconductor wafer 1x and arranged in parallel. The semiconductor device 91 illustrated in FIG. 6A may be, for example, the semiconductor device 90 in which the IGBT illustrated in FIGS. 7 and 8 is formed, or illustrated in FIGS. 6B and 6C. The semiconductor devices 92 and 93 may be used. In both the semiconductor devices 92 and 93 shown in FIGS. 6B and 6C, the line-shaped dummy element portion Tde is arranged in the same line direction with respect to the line-shaped gate element portion Tg. . The semiconductor device 91 shown in FIG. 6A is not limited to this, and may be, for example, the semiconductor devices 100 to 107 shown in FIGS.

  In the semiconductor wafer 1x of FIG. 6A, the line-shaped gate element portions Tg of the unit configuration regions 1c of the semiconductor devices 91 arranged adjacent to each other have different line directions (line directions substantially perpendicular to each other). . Moreover, the unit structure area | region 1c arrange | positioned adjacent to which has mutually different line directions is arrange | positioned at checkered pattern shape.

  In the semiconductor wafer 1x of FIG. 6A, the line-shaped gate element portions Tg of the unit configuration regions 1c of the semiconductor devices 91 arranged adjacent to each other have different line directions. Therefore, in the semiconductor wafer 1x, at least two unit configuration regions 1c having different line directions exist. For this reason, not all the line-shaped gate element portions Tg are aligned in a specific line direction on the semiconductor wafer 1x. Therefore, the semiconductor wafer 1x shown in FIG. 6A is a semiconductor wafer that hardly warps even after the trench is formed. Further, the semiconductor device 91 manufactured by cutting out from the semiconductor wafer 1x can also be a semiconductor device in which warpage due to the trench gate hardly occurs.

  In addition, the semiconductor wafer 1x in FIG. 6A is easily transported to the subsequent process, hardly breaks or falls, and hardly causes exposure defects and processing defects such as polishing and cutting. For this reason, the semiconductor device 91 manufactured by cutting out from the semiconductor wafer 1x can be an inexpensive semiconductor device with a high yield.

  The thickness of the semiconductor wafer 1x may be 300 μm or less, particularly 150 μm or less, which can achieve both the prevention of warpage and the improvement of characteristics when the IGBT is formed.

  As described above, the semiconductor device and the semiconductor wafer described above are a semiconductor device and a semiconductor wafer in which a transistor having a trench gate structure is formed, and the semiconductor device and the semiconductor wafer are less likely to be warped by the trench gate. ing.

1 is a schematic plan view of a semiconductor device 100 as an example of the semiconductor device of the present invention. (A), (b) is an example of another semiconductor device, and is a typical top view of semiconductor devices 101 and 102, respectively. (A), (b) is an example of another semiconductor device, and is a typical top view of semiconductor devices 103 and 104, respectively. FIG. 6 is a schematic cross-sectional view of a semiconductor device 105 as another semiconductor device example. (A), (b) is an example of another semiconductor device, and is a typical top view of semiconductor devices 106 and 107, respectively. In the example of the semiconductor wafer of the present invention, (a) is a schematic plan view of the semiconductor wafer 1x. (B), (c) is another example of the semiconductor device 91 formed in the semiconductor wafer 1x of (a), and is a schematic plan view of the semiconductor devices 92, 93, respectively. It is typical sectional drawing of the semiconductor device 90 by which IGBT of trench gate structure is comprised with the conventional semiconductor device. FIG. 8 is a plan view illustrating a typical arrangement example of the main part of the semiconductor device 90 illustrated in FIG. 7 with respect to the semiconductor chip 1c. (A) is a typical top view of the conventional semiconductor wafer 1w before cutting out the semiconductor chip 1c in which the semiconductor device 90 shown in FIG. 8 was formed, (b) is a dashed-dotted line A- in (a). It is sectional drawing in A.

Explanation of symbols

90 to 93, 100 to 107 Semiconductor device 1c Semiconductor chip, unit configuration region 1w, 1x Semiconductor wafer Te, Tg Line-shaped gate element portion Pa to Pd Gate element portion parallel set 12 Impurity diffusion region (semiconductor layer)
12a First divided region (fixed potential region)
12b Second divided region (floating potential region)
Tda ~ Tde Line-shaped dummy element

Claims (15)

A semiconductor device in which a transistor having a trench gate structure is formed on a semiconductor chip,
The trench gate of the transistor comprises a plurality of line-shaped gate element portions formed in a surface layer portion of the semiconductor chip,
The line-shaped gate element portions arranged side by side constitute a gate element portion parallel set, and a plurality of sets of the gate element portion parallel sets are arranged on the surface layer portion of the semiconductor chip,
2. A semiconductor device, wherein the gate element portions arranged adjacent to each other in a parallel set of line-shaped gate element portions have different line directions.   2. The semiconductor device according to claim 1, wherein the gate element portions arranged in parallel to each other in the parallel set of line-shaped gate element portions have line directions substantially orthogonal to each other.   3. The semiconductor device according to claim 1, wherein the gate element part parallel sets arranged adjacent to each other having different line directions are arranged in a checkered pattern. 4.   The semiconductor device according to claim 1, wherein the transistor is an IGBT. A semiconductor device in which an IGBT having a trench gate structure is formed on a semiconductor chip,
The trench gate of the IGBT is formed in a surface layer portion of the semiconductor chip, and includes a plurality of line-shaped gate element portions arranged in parallel,
A predetermined impurity diffusion region selectively formed in a surface layer portion of the semiconductor chip is divided into a plurality of regions by the plurality of line-shaped gate element portions,
Of the plurality of divided regions, when a divided region to which the emitter electrode of the IGBT is connected is a first divided region, and a divided region to which the emitter electrode of the IGBT is not connected is a second divided region, the first divided region and Second divided regions are arranged alternately in the surface layer portion of the semiconductor chip,
A plurality of parallel line-shaped dummy element portions having the same cross-sectional structure as the trench gate are arranged in the second dividing region in a line direction different from the line-shaped gate element portion. .   6. The semiconductor device according to claim 5, wherein the line-shaped gate element portion and the line-shaped dummy element portion have line directions substantially orthogonal to each other.   6. The semiconductor device according to claim 5, wherein the line of the line-shaped dummy element portion has a ring shape.   The semiconductor device according to claim 1, wherein a thickness of the semiconductor chip is 300 μm or less.   The semiconductor device according to claim 8, wherein a thickness of the semiconductor chip is 150 μm or less. A plurality of unit configuration regions of a semiconductor device are semiconductor wafers arranged,
The semiconductor device is a semiconductor device in which a transistor having a trench gate structure is formed,
A trench gate of the transistor is formed in a surface layer portion of the semiconductor wafer, and includes a plurality of line-shaped gate element portions arranged in parallel;
A semiconductor wafer characterized in that the line-shaped gate element portions of the unit constituent regions arranged adjacent to each other have different line directions.   11. The semiconductor wafer according to claim 10, wherein the line-shaped gate element portions of the unit configuration regions arranged adjacent to each other have line directions substantially orthogonal to each other.   12. The semiconductor wafer according to claim 10 or 11, wherein the unit constituting regions arranged adjacent to each other having different line directions are arranged in a checkered pattern.   The semiconductor wafer according to claim 10, wherein the transistor is an IGBT.   The semiconductor wafer according to claim 10, wherein a thickness of the semiconductor wafer is 300 μm or less.   The semiconductor wafer according to claim 14, wherein a thickness of the semiconductor wafer is 150 μm or less.

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