JP2008227205A - Semiconductor device and manufacturing method therefor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a structure in which driving capability of p-type MOS transistors can be enhanced, chipping by dicing can be prevented, and positional accuracy of the MOS transistors during formation thereof can be improved. <P>SOLUTION: The semiconductor device having a semiconductor wafer 11 that has a ä001} surface as the main surface and a position determining unit indicating a <100> direction comprises a plurality of p-channel type MOS transistors P and n-channel type MOS transistors N formed on the semiconductor wafer 11. In addition, scribe lines 13 disposed on the semiconductor wafer 11 in a matrix shape is set to scribe in a <110> direction, and the channel direction of the p-channel type MOS transistors P is the <100> direction. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device including an n-channel MOS transistor and a p-channel MOS transistor on a semiconductor wafer and a method for manufacturing the same.

  In recent years, with the progress of the digital society, there is an increasing demand for miniaturization, high functionality, and high speed operation of semiconductor devices, and semiconductor devices have been integrated on a large scale. While the miniaturization of MOS transistors is progressing for the purpose of increasing the speed of semiconductor devices, there is a problem that the driving ability of the transistors is lowered due to the influence of the high electric field effect and the short channel effect due to the shortening of the gate length.

In order to solve this problem, in a semiconductor device provided with an n-channel MOS transistor and a p-channel MOS transistor, the channel direction of each MOS transistor has been formed in the <110> direction so far. A semiconductor device provided with a p-channel MOS transistor with improved driving capability has been realized by forming it in the direction (see, for example, Patent Document 1). In this conventional semiconductor device, the effective mass of holes in the semiconductor (silicon) is anisotropic, the effective mass is lighter in the <100> direction than in the <110> direction, and the carrier mobility is increased. This is a property that uses this property.
JP 2003-197906 A

  For example, as shown in FIGS. 9A and 9B, the direction of the notch 141 used for positioning in the semiconductor wafer diffusion process (hereinafter referred to as the notch direction) or the direction of the orientation flat (hereinafter referred to as the orientation flat direction). Using the semiconductor wafer 11 set in the <100> direction, the channel direction in each n-channel MOS transistor N and p-channel MOS transistor P formed on each chip 12 is set to <100> as shown in the region C1. When the direction is set, the direction of the scribe line 13 in the semiconductor wafer 11 (hereinafter referred to as “scribe direction” defined later) is a <100> direction, and the direction is a cleavage plane {110 of the semiconductor wafer (silicon). } In the direction of 45 ° to the dicing of the semiconductor wafer Mappings are easily generated, there is a problem that causes a generation or deterioration of the reliability of the crack during assembly.

  On the other hand, in order to prevent chipping at the time of dicing, for example, as shown in FIGS. 10A and 10B, the notch direction (direction of the notch 141) in the semiconductor wafer 11 is set to the <110> direction, and scribe is performed. The direction (direction of the scribe line 13) is set to the <110> direction, and the channel in each n-channel MOS transistor N and p-channel MOS transistor P formed on each chip 12 as shown in the region B1. A method of setting the direction to the <100> direction is conceivable. However, in this case, as shown in FIG. 10A, when photolithography is performed using a stepper including a wafer fixing stage 27 and a reduction exposure machine 28, laser light is applied to the reticle 26 on which a circuit design pattern is formed. The light is transmitted and exposed onto the semiconductor wafer 11 through the lens 29. As shown in the drawing, the reticle direction of the reticle 26 and the moving direction of the wafer fixing stage 27 are both <110> directions. Here, since the stepper performs correction in the notch direction and the 90 ° direction thereof, the positional accuracy in the <100> direction of 45 ° with respect to the notch direction is deteriorated. Accordingly, as shown in FIG. 10B, in the conventional semiconductor device, the MOS transistor is formed at a direction of 45 ° with respect to the notch direction, so that the positional accuracy is deteriorated and the reliability is deteriorated due to characteristic variation. In addition, there is a problem that the probability of occurrence of a defect due to a short circuit between adjacent MOS transistors increases.

  In view of the above, an object of the present invention is to provide a semiconductor device having a structure capable of realizing improvement in driving capability of a p-channel MOS transistor, prevention of chipping by dicing, and improvement in positional accuracy during formation of the MOS transistor, and its manufacture Is to provide a method.

  A semiconductor device according to one embodiment of the present invention is a semiconductor device including a semiconductor wafer having a {001} plane as a main surface and a position determining unit indicating a <100> direction, and is formed on the semiconductor wafer. A plurality of p-channel MOS transistors and a plurality of n-channel MOS transistors, the direction of the scribe line provided on the semiconductor wafer is the <110> direction, and the channel direction in the p-channel MOS transistor is <100 > Direction.

  Thus, according to the semiconductor device of one embodiment of the present invention, the direction indicated by the position determining unit is the <100> direction, and the channel direction of the p-channel MOS transistor is the <100> direction. The hole mobility in the p-channel MOS transistor is improved efficiently. Therefore, the driving capability of the p-channel MOS transistor can be improved. Furthermore, since the direction of the scribe line is the <110> direction, the semiconductor wafer can be diced in the cleavage direction, and chipping during cutting can be prevented.

  A semiconductor device according to one embodiment of the present invention includes a plurality of unit cells each including a p-channel MOS transistor and an n-channel MOS transistor, and the plurality of unit cells are repeatedly arranged in parallel to the <110> direction. It is preferable. Thereby, since the unit cells are arranged in the direction equal to the scribe direction <110>, the area ratio (occupancy) of the unit cells on the chip can be improved and the design efficiency can be improved.

  In the semiconductor device according to one embodiment of the present invention, the channel direction in the n-channel MOS transistor is preferably set to the <100> direction. As a result, the channel directions of the p-channel MOS transistor and the n-channel MOS transistor are all in the <100> direction, so that the chip area ratio can be efficiently reduced.

  A manufacturing method of a semiconductor device according to an embodiment of the present invention includes a semiconductor wafer having a {001} plane as a main surface and a position determining unit indicating a <100> direction and a scribe line in a <110> direction. A method of manufacturing a semiconductor device, comprising: forming a plurality of p-channel MOS transistors on a semiconductor wafer; and forming a plurality of n-channel MOS transistors, and forming a p-channel MOS transistor Is characterized in that the p-channel MOS transistor is formed so that the channel direction of the p-channel MOS transistor is the <100> direction.

  According to such a method for manufacturing a semiconductor device, the position determining unit is set in the <100> direction and the channel direction of the p-channel MOS transistor is set to <100>, so that the hole mobility is Since the channel direction is improved as compared with the conventional example in which the <110> direction is set, the driving capability of the p-channel MOS transistor is improved. Furthermore, since the scribe direction is set to the <110> direction, the semiconductor wafer can be diced in the cleavage direction, so that chipping can be prevented.

  In the method for manufacturing a semiconductor device according to one embodiment of the present invention, the step of forming a p-channel MOS transistor and the step of forming an n-channel MOS transistor are steps using a stepper provided with a reticle, The direction is the same as that of the stage on which the semiconductor wafer is mounted, and the direction is <100>.

  According to such a method for manufacturing a semiconductor device of the present invention, it is only necessary to change the position determining portion of the semiconductor wafer in the <100> direction, and a stepper which is a semiconductor manufacturing apparatus conventionally used for the present invention is used as it is. Can be used. Therefore, the development cost and time for new equipment can be reduced. Further, since the p-channel MOS transistor P is formed by moving the wafer process stage in the <100> direction using a reticle in which the <100> direction of the semiconductor wafer is the reticle direction, the stepper accuracy correction direction, that is, the position determination is determined. The MOS transistor can be formed in the direction <100> of the portion, and the positional accuracy can be improved.

  In the method for manufacturing a semiconductor device according to one embodiment of the present invention, the step of forming a p-channel MOS transistor and the step of forming an n-channel MOS transistor are steps using a stepper provided with a reticle, The direction is set to the <110> direction, and the moving direction of the stage on which the semiconductor wafer is mounted is set to the <100> direction.

  According to such a method, the reticle direction is parallel to the arrangement direction of the semiconductor chip and the direction of the side, so that the reticle can be used effectively and can be an exposure target when the same size reticle is used. The number of chips increases to reduce the number of exposures, and the exposure can be performed efficiently. Further, since the p-channel MOS transistor is formed by moving the wafer process stage in the <100> direction using a reticle whose <100> direction is the reticle direction, the stepper accuracy correction direction, that is, the position determination unit The MOS transistor can be formed in the direction <100>, and the positional accuracy can be improved.

  According to the semiconductor device and the manufacturing method thereof according to an aspect of the present invention, the position determination unit of the semiconductor wafer is in the <100> direction, and the channel direction of the p-channel MOS transistor is in the <100> direction. Carrier mobility is increased, and the driving capability of the p-channel MOS transistor can be improved. Furthermore, since the scribe direction is set to the <110> direction, the semiconductor wafer can be diced in the cleavage direction, so that chipping can be prevented. As a result, it is possible to provide a semiconductor device that can realize high functionality and improved reliability.

  Hereinafter, as a premise for explaining an embodiment of the present invention, definitions of terms used in the present application will be described with reference to FIGS. 1 (a) and (b), FIG. 2, and FIG.

  In general, a semiconductor device is manufactured by arranging a large number of IC circuits composed of a plurality of elements and having a predetermined function in a matrix on a semiconductor wafer such as silicon.

  FIGS. 1A and 1B are plan views of a general semiconductor wafer 11. As shown in FIGS. 1A and 1B, a large number of semiconductor chips (chip regions) 12 on the semiconductor wafer 11 are separated from each other by scribe lines 13 provided in a mesh shape. After a large number of semiconductor chips 12 are formed on one semiconductor wafer 11 through a semiconductor manufacturing process, the semiconductor wafer 11 is diced into individual chips along a scribe line 13 to form a semiconductor device. .

  Further, a notch 141 shown in FIG. 1 (a) or an orientation flat 142 shown in FIG. 1 (b) is provided on the outer peripheral portion of the semiconductor wafer 11, so that a diffusion process such as lithography or etching can be performed at the wafer level. It serves as a mark for alignment in the wafer direction during the inspection process or dicing process. In the present invention, it is referred to as a position determining unit.

  Next, the “wafer direction”, “notch direction”, “orientation flat direction”, and “scribe direction” in the present invention will be described. “Wafer direction”, “notch direction”, and “orientation flat direction” all mean the same direction. Specifically, as shown in FIGS. 1A and 1B, the semiconductor wafer 11 Means a direction from the center of the notch 141 toward the center of the notch 141 or the orientation flat 142. The “scribe direction” means the direction of the scribe line 13 and parallel to each side of the rectangular semiconductor chip 12, as shown in FIGS. A cutting device such as a dicing blade in the process coincides with the scanning direction on the semiconductor wafer 11.

  As described above, the “wafer direction”, “notch direction”, “orientation flat direction”, and “scribe direction” are defined. As will be described later with reference to FIG. Since the semiconductor wafer (the silicon crystal constituting the surface) is 90 ° rotationally symmetric, the above “wafer direction”, “notch direction”, “orientation flat direction”, and “scribe direction” are equivalent directions. Needless to say, there exists. The “reticle direction” is defined later, but the same applies to the “reticle direction”.

  FIG. 2 is a schematic diagram for explaining the crystal structure and crystal orientation of silicon generally used as the semiconductor wafer 11. As shown in FIG. 2, the silicon crystal has a so-called diamond structure, and when the directions are arranged in a face-centered cubic lattice starting from silicon atoms, the X direction, the Y direction, and the Z direction Are defined as [100] direction, [010] direction and [001] direction, respectively. Further, when a certain plane is considered, in the physical physics, the crystal direction of the normal is defined as the plane orientation, and for example, the plane indicated by the oblique lines in FIG. 2 is defined as the (001) plane. A direction forming 45 ° with respect to the [100] direction and the [010] direction is defined as a [110] direction. The [110] direction is the cleavage direction of the silicon crystal, and is the direction in which cracks are easily formed while the direction is easy to cleave.

  Here, since the silicon crystal having the diamond structure has a 90 ° rotationally symmetric structure, the [100] direction, the [010] direction, the [001] direction, and the six directions including these minus directions are synonymous with each other. Therefore, it is collectively referred to as the <100> direction. Also, the [110] direction, the [101] direction, the [011] direction, and the 12 directions including these minus directions are also synonymous with each other, and are collectively referred to as the <110> direction.

  Similarly, in the present application, the crystal plane is defined by a method according to the above-described physical physics, and the {001} plane is referred to as the (001) plane, the (010) plane, the (100) plane, and these. 6 faces including the minus direction.

  FIG. 3 shows a schematic plan view and a cross-sectional view of the MOS transistor. As shown in FIG. 3, whether the MOS transistor is a p-channel MOS transistor or an n-channel MOS transistor, a gate electrode 21 formed on the semiconductor wafer 11 via a gate insulating film 24; A source region 22 formed under the gate electrode 21 in the semiconductor wafer 11 (p-type source region doped p-type for a p-channel MOS transistor, n-type doped for an n-channel MOS transistor) N-type source region) and drain region 23 (p-type doped p-type drain region for a p-channel MOS transistor, n-type doped n-type drain region for an n-channel MOS transistor) It has the composition provided with.

  In the MOS transistor having the above configuration, the “channel direction” means a direction from the source region 22 toward the drain region 23 regardless of whether it is a p-channel MOS transistor or an n-channel MOS transistor. Needless to say, there is an equivalent direction for the channel direction as well.

(First embodiment)
The semiconductor device according to the first embodiment of the present invention will be described below with reference to FIG.

  FIGS. 4A and 4B are plan views of main parts of the semiconductor device according to the first embodiment of the present invention. FIG. 4A shows a semiconductor wafer, and FIG. FIG. 5 is an enlarged view of a predetermined area (A1) in FIG.

  As shown in FIG. 4A, a semiconductor wafer 11 having a {001} plane as a main surface is provided with a plurality of semiconductor chips 12 in a matrix, and the plurality of semiconductor chips 12 are scribed so as to be separated from each other. A line 13 is provided, and a notch 141 (position determining unit of the present invention) used for determining the position of the semiconductor wafer 11 is further provided. Further, as shown in FIG. 4B, the semiconductor chip 12 includes a plurality of p-channel MOS transistors P and n-channel MOS transistors N having the general structure shown in FIG.

  Here, as shown in FIGS. 4A and 4B, in this embodiment, the direction of the notch 141 (notch direction) is set to the [100] direction, and the direction of the scribe line 13 (scribe direction). Is set in the [110] direction.

  As described above, the notch direction may be the <100> direction equivalent to the [100] direction, and similarly, the scribe direction may be the <110> direction equivalent to the [110] direction.

  4A illustrates the case where the notch 141 is used, but the orientation flat direction is also provided when an orientation flat is provided as shown in FIG. 1B instead of the notch 141. Is set in the <100> direction.

  Further, as shown in FIG. 4B, the channel directions of the p-channel MOS transistor P and the n-channel MOS transistor N are set to the [100] direction or the [010] direction. That is, the channel direction of each MOS transistor has a <100> direction.

  Here, in each semiconductor chip 12, only the p-channel MOS transistor P whose drive capability is to be improved can be arranged so that the channel direction is the <100> direction. However, it is more preferable to arrange all the p-channel MOS transistors P so that the channel direction is the <100> direction, and the driving capability can be further improved.

  Further, the channel direction of the n-channel MOS transistor N is set to the <100> direction in the present embodiment, but may be a different direction such as the <110> direction, for example. Or may include different directions.

  As described above, according to the semiconductor device of one embodiment of the present invention, the notch direction is set to the <100> direction and the channel direction of the p-channel MOS transistor P is set to the <100> direction. Since the mobility of carriers (here, holes) is improved as compared with the conventional semiconductor device in which the channel direction is set to the <110> direction, the driving capability of the p-channel MOS transistor P is improved. Furthermore, since the scribe direction is set to the <110> direction, dicing in the cleavage plane direction of the semiconductor wafer can be performed, and chipping can be prevented.

(First modification)
Hereinafter, a first modification of the semiconductor device according to the first embodiment of the present invention described above will be described with reference to FIG. FIG. 5A shows a plan view of the semiconductor wafer according to the first modification, and FIG. 5B is an enlarged view of a predetermined region (A2) in FIG. 5A.

  Unlike the semiconductor device according to the first embodiment shown in FIG. 4B, in the first modification, as shown in FIG. 5B, a p-channel MOS transistor P and an n-channel MOS transistor N are used. A plurality of rectangular unit cells 31 composed of the above are repeatedly arranged in a matrix parallel to the <110> direction.

  Furthermore, the channel directions of all p-channel transistors P and n-channel transistors N are aligned in the same direction ([010]).

  As shown in FIGS. 5A and 5B, in the first modification, as shown in the semiconductor chip 12 in the region A2 on the semiconductor wafer 11, a p-channel MOS transistor P and an n-channel MOS transistor N are used. And a plurality of rectangular or square unit cells 31 constituted by a logic circuit such as an inverter or NAND, or a memory circuit such as SRAM, and each unit cell 31 is repeated in the <110> direction. Are arranged.

  Due to such a configuration, a larger number of MOS transistors can be arranged on the semiconductor chip 12 than in FIG. 4B, so that efficient design in units of core cells or logic cells becomes possible. In addition, a dense MOS transistor without a dead space can be arranged.

  In particular, since the p-channel MOS transistor P and the n-channel MOS transistor N (in the channel direction) are arranged so as to be inclined by 45 ° with respect to each side of the semiconductor chip 12, the unit shown in FIG. When the cell 31 rotated by 45 ° is disposed on the semiconductor chip 12, the dead space that occurs can be eliminated. In addition, in order to eliminate the dead space, it is possible to avoid poor design efficiency due to the need for another cell having a different shape. In addition, the driving capability of the LSI total p-channel MOS transistor can be improved efficiently.

  The channel directions of the p-channel MOS transistor P and the n-channel MOS transistor N are set to the <100> direction so that the driving power of the p-channel MOS transistor P is improved. Further, by setting the channel direction of the n-channel transistor N to be the <100> direction, the area efficiency can be improved and the processing accuracy of the N-channel transistor can be improved.

(Second modification)
Next, a second modification of the semiconductor device according to the first embodiment will be described with reference to FIG. FIG. 6A is a plan view of a semiconductor wafer in a second modification of the semiconductor device according to the first embodiment of the present invention, and FIG. 6B is a predetermined view in FIG. It is an enlarged view of a field (A3). However, the description of the same parts as those of the first embodiment and the first modification is omitted.

  As shown in FIGS. 6A and 6B, the second modification is different from the first modification described above, as shown in the semiconductor chip 12 in the region A3 on the semiconductor wafer 11, as shown in FIG. The channel directions of the transistors P are all set in the <100> direction, while the channel directions of the n-channel MOS transistors N are all set in the <110> direction.

  In this case, since the channel direction is the <100> direction in the p-channel MOS transistor, the mobility of holes as carriers is maximized, and in the n-channel MOS transistor, the channel direction is <110>. The direction has higher mobility of electrons as carriers than the <100> direction. Therefore, according to the second modification, the driving capability of the p-channel MOS transistor and the n-channel MOS transistor can be improved most efficiently, and the n-channel generally has a smaller area than the p-channel MOS transistor. It is possible to contribute to miniaturization by improving the driving capability of the MOS transistor.

(Second Embodiment)
Hereinafter, as a second embodiment, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to the drawings. However, detailed description of the same parts as those in the first embodiment will be omitted.

  FIGS. 7A and 7B are views for explaining a method for manufacturing a semiconductor device according to the present embodiment. FIG. 7A is a schematic diagram of the stepper according to the present embodiment. FIG. 7B is an enlarged plan view of a predetermined region (B1) in FIG.

  As shown in FIG. 7A, by using a photolithography technique using a stepper including a reduction exposure machine 28 and a wafer fixing stage 27, for example, the region B1 of the semiconductor wafer 11 in which the notch direction is set to the [100] direction. A p-channel MOS transistor P and an n-channel MOS transistor N are formed on the semiconductor chip 12 in the (reticle projection region 26a). Here, the region B1 includes a plurality of semiconductor chips 12 shown in FIG.

  Specifically, a laser beam is transmitted through a reticle 26 on which a circuit design pattern is formed, and exposed on a semiconductor wafer 11 through a lens 29, thereby forming a p-channel MOS transistor P and an n-channel MOS transistor N. To do. By moving the wafer fixing stage 27, a p-channel MOS transistor P and an n-channel MOS transistor N are sequentially formed. Here, the p-channel MOS transistor P is formed so that the channel direction of the p-channel MOS transistor P is the notch direction, that is, the [100] direction. The direction of the reticle 26 (reticle direction) and the moving direction of the wafer fixing stage 27 are both set to the <100> direction. Furthermore, the pattern of the scribe line 13 is formed so that the scribe direction is 45 ° with respect to the notch direction, that is, the <110> direction.

  Note that the reticle direction refers to a direction connecting a pair of sides facing each other among the four sides of a square shape.

  According to the present embodiment, since an existing stepper used for manufacturing a semiconductor device can be used as it is, it is possible to reduce the cost and time required for development by supplying new equipment, and to reduce the semiconductor wafer 11 to <100. Since the p-type MOS transistor P and the n-channel MOS transistor N are formed by moving the wafer process stage 27 in the <100> direction using the reticle 26 in which the> direction is the reticle direction, MOS transistors can be formed in the <100> direction of the stage movement direction, and the positional accuracy can be maintained.

  It goes without saying that the method for manufacturing a semiconductor device according to the present embodiment can be applied to the semiconductor devices according to the first and second modifications as described above.

(Modification)
Hereinafter, a modification of the semiconductor device manufacturing method according to the second embodiment will be described with reference to FIG. FIG. 8A is a schematic diagram of a stepper according to this modification, and FIG. 8B is an enlarged plan view of a predetermined region (B2) in FIG. 8A. However, detailed description of the same parts as those in the second embodiment will be omitted.

  As shown in FIG. 8A, in this modification as well, the notch direction is set to the <100> direction by using a photolithography technique with a stepper including a reduction exposure machine 28 and a wafer fixing stage 27. A plurality of p-channel MOS transistors P and n-channel MOS transistors N are formed on the semiconductor chip 12 in, for example, the region B2 (reticle projection region 26a) of the semiconductor wafer 11 being formed. Thereby, as compared with FIG. 7, a larger number of transistors can be arranged in a predetermined reticle projection region.

  This modification differs from the semiconductor device manufacturing method according to the second embodiment described above in that the reticle direction is set to the <110> direction as shown in FIGS. 8A and 8B. It is.

  Therefore, in the present modification, the reticle direction is parallel to the arrangement direction of the semiconductor chip 12 and the direction of the side of the reticle projection region 26a, so that the reticle 26 can be used effectively and the same size reticle is used. In this case, the number of chips that can be exposed is increased, the number of exposures is reduced, and the exposure can be performed efficiently. On the other hand, in the second embodiment, since the scribe direction with respect to the reticle direction, that is, the direction in which the semiconductor chip 12 is formed with respect to the reticle direction has an inclination of 45 °, a dead space is formed at the corner of the reticle projection region 26a. In this case, a dead area is generated in the reticle 26 (reticle projection area 26a). However, according to the present modification, this dead space can be eliminated.

  When the reticle 26 is manufactured, it is preferable that the reticle manufacturing apparatus itself is also rotated by 45 ° and then the reticle 26 is manufactured. In this way, in the reticle manufacturing process, the alignment direction of the reticle manufacturing apparatus is adjusted. Since the directions of the source and drain in the reticle coincide with each other, the production accuracy of the reticle itself improves.

  The present invention described above is effective for a semiconductor device using a fragile wiring interlayer film such as a low-k film that is likely to cause chipping during dicing.

  The present invention is useful for a semiconductor device that includes a p-channel MOS transistor and uses a miniaturization process in which driving capability is reduced due to the short channel effect.

(A) And (b) is a top view which shows the structure of a common semiconductor wafer. 1 is a schematic diagram for explaining a crystal structure and crystal orientation of silicon generally used as a semiconductor wafer 11. FIG. It is the schematic plan view and sectional drawing of a MOS transistor provided with the general structure. (A) has shown the semiconductor wafer in the 1st Embodiment of this invention, (b) is an enlarged view of the predetermined area | region (A1) in (a). (A) has shown the top view of the semiconductor wafer in the 1st modification of the semiconductor device which concerns on the 1st Embodiment of this invention, (b) has expanded the predetermined area | region (A2) in (a). FIG. FIG. 6A is a plan view of a semiconductor wafer in a second modification of the semiconductor device according to the first embodiment of the present invention, and FIG. 6B is a diagram illustrating a predetermined region in FIG. It is an enlarged view of A3). (A) is a schematic diagram of the stepper according to the second embodiment, and (b) is an enlarged plan view of a predetermined region (B1) in (a). (A) is a schematic diagram of the stepper which concerns on the modification of the semiconductor device which concerns on 2nd Embodiment, (b) is an enlarged plan view of the predetermined area | region (B2) in (a). (A) And (b) is a top view which shows the structure of the semiconductor device for demonstrating the conventional subject. (A) And (b) is a figure for demonstrating the manufacturing method of the semiconductor device for demonstrating the conventional subject.

Explanation of symbols

11 Semiconductor wafer 12 Semiconductor chip 13 Scribe line 141 Notch 142 Orientation flat 21 Gate electrode 22 Source region 23 Drain region 24 Gate insulating film 26 Reticle 26a Reticle projection region 27 Wafer fixing stage 28 Reduction exposure device 29 Lens N n-channel MOS transistor P p-channel MOS transistor 31 repetitive unit cell

Claims (6)

A semiconductor device including a semiconductor wafer having a {001} plane as a main surface and a position determining unit indicating a <100> direction,
A plurality of p-channel MOS transistors and a plurality of n-channel MOS transistors formed on the semiconductor wafer;
The direction of the scribe line provided on the semiconductor wafer is the <110> direction,
The semiconductor device according to claim 1, wherein a channel direction in the p-channel MOS transistor is a <100> direction. The semiconductor device according to claim 1,
A plurality of unit cells composed of the p-channel MOS transistor and the n-channel MOS transistor;
The semiconductor device, wherein the plurality of unit cells are repeatedly arranged in parallel to the <110> direction. The semiconductor device according to claim 2,
A semiconductor device in which a channel direction in the n-channel MOS transistor is set to a <100> direction. A method of manufacturing a semiconductor device comprising a semiconductor wafer having a {001} plane as a main surface and a position determining unit indicating a <100> direction and a scribe line in a <110> direction,
Forming a plurality of p-channel MOS transistors on the semiconductor wafer; and forming a plurality of n-channel MOS transistors.
The step of forming the p-channel MOS transistor includes forming the p-channel MOS transistor so that a channel direction of the p-channel MOS transistor is a <100> direction. Method. In the manufacturing method of the semiconductor device according to claim 4,
The step of forming the p-channel MOS transistor and the step of forming the n-channel MOS transistor include:
Using a stepper with a reticle,
A method of manufacturing a semiconductor device, wherein a reticle direction of the reticle and a moving direction of a stage on which the semiconductor wafer is mounted are equal to each other and are <100> directions. In the manufacturing method of the semiconductor device according to claim 4,
The step of forming the p-channel MOS transistor and the step of forming the n-channel MOS transistor include:
Using a stepper with a reticle,
While setting the reticle direction of the reticle to the <110> direction,
A method of manufacturing a semiconductor device, wherein a moving direction of a stage on which the semiconductor wafer is mounted is set to <100>.

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