JP2014146829A - Semiconductor chip and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce or prevent defect in shape caused by cutting in a disconnection process of a semiconductor wafer using stealth dicing.SOLUTION: In the case of dividing a semiconductor wafer 1W by stealth dicing, pads 1LBt for testing of a cutting region CR and an alignment target Am are arranged on one side of the cutting region CR in a width direction, and laser beams for forming a modified region PR are irradiated on a position away from the pads 1LBt for testing and the alignment target Am in planar view. By doing this, defect in shape caused by cutting in a disconnection process of the semiconductor wafer using stealth dicing can be reduced or prevented.

Description

  The present invention relates to a semiconductor device manufacturing method and semiconductor device technology, and more particularly to a semiconductor wafer dicing technology.

  In recent years, with the reduction in size and weight of mobile devices represented by mobile phones and digital cameras, and information storage media represented by memory cards, semiconductor chips incorporated in these devices have been made thinner. For this reason, in the dicing process, individual thin semiconductor chips are obtained by cutting the thin semiconductor wafer. However, when the blade dicing method is used in this dicing process, the semiconductor wafer is thin, so that the semiconductor chip is easily chipped and thin. There is a problem that the bending strength of the semiconductor chip is significantly reduced. From the viewpoint of improving the operation speed of a semiconductor device, there is a product that uses a low dielectric constant film (so-called Low-k film) whose dielectric constant is lower than that of silicon oxide as a wiring interlayer insulating film of a semiconductor chip. Some K films are brittle and easy to peel off, and some have fine bubbles inside, and the blade dicing method may not cut well.

  Therefore, stealth dicing (registered trademark) has been attracting attention as a new dicing method that avoids these problems. This stealth dicing method is a dicing method in which a laser beam is irradiated inside a semiconductor wafer to selectively form a modified layer, and the semiconductor wafer is cut using the modified layer as a division starting point. According to this method, even an extremely thin semiconductor wafer having a thickness of about 30 μm can be directly cut without physically applying stress, so that chipping can be reduced and reduction in the bending strength of the semiconductor chip can be suppressed. In addition, regardless of the thickness of the semiconductor wafer, high-speed dicing at 300 mm or more per second is possible, so that throughput can be improved. Therefore, the stealth dicing method is an essential technique for thinning the semiconductor chip.

  Such stealth dicing technology is described in, for example, Japanese Patent Application Laid-Open No. 2004-221286 (Patent Document 1). Paragraph 0022 and FIG. 1 of Patent Document 1 disclose a configuration in which a wiring layer is provided on both sides of a test pad in an area between chips. This wiring layer does not perform electrical coupling, but is a dummy pattern for making the laser beam irradiation area uniform and facilitating absorption of the laser beam. Further, paragraph 0023 of Patent Document 1 discloses a method of melting and cutting a semiconductor wafer by irradiating a region where the wiring layer is formed with a laser beam when dividing the semiconductor wafer. Further, in paragraph 0024 of this Patent Document 1, in the division of the semiconductor wafer, the focus position of the laser beam is aligned with the inside of the semiconductor wafer to form a melt processing region by multi-grating absorption, and then the semiconductor wafer is subjected to cracking or expanding. Is disclosed.

  Further, for example, in Japanese Patent Application Laid-Open No. 2005-340426 (Patent Document 2), a groove is formed in a test bonding pad on a main surface of a semiconductor wafer, and then a tape is attached to the main surface of the semiconductor wafer. A stealth dicing technology is used to form a modified layer inside a semiconductor wafer by irradiating a laser beam from the back side of the wafer, and then to divide the semiconductor wafer into individual semiconductor chips starting from the modified layer by stretching the tape. It is disclosed.

  Further, for example, in Japanese Patent Application Laid-Open No. 2005-32903 (Patent Document 3), a test electrode pad or the like on a main surface of a semiconductor wafer is removed with a blade, and then laser light is irradiated from the main surface side of the semiconductor wafer. A stealth dicing technique is disclosed in which a modified layer is formed inside a semiconductor wafer, and then a dicing tape is stretched to divide the semiconductor wafer into individual semiconductor chips starting from the modified layer.

Japanese Patent Laying-Open No. 2004-221286 (paragraphs 0022 to 0024 and FIG. 1) JP 2005-340426 A JP 2005-32903 A

  However, the present inventor has found that the stealth dicing method has the following problems.

  First, the present inventor examined the case of using the expanding method when dividing the semiconductor wafer in the stealth dicing method. This expanding method is a method of dividing a semiconductor wafer into individual semiconductor chips by extending a resin sheet on which the semiconductor wafer is attached in a direction from the center of the semiconductor wafer toward the outer periphery. By the way, a test pad made of, for example, aluminum is arranged in the dicing area. In the case of the expand system, when the test pad is extended and cut, the test pad is formed on the cut surface portion. There is a problem that a whisker-like conductor wire is formed.

  Therefore, the present inventor adopted a bending method instead of the expanding method. This bending method is a method in which a semiconductor wafer is divided into individual semiconductor chips by bending the semiconductor wafer by applying a force in a direction intersecting the main surface of the semiconductor wafer. In the case of this method, the problem of forming the whisker-like conductor wire is reduced. However, as shown in FIG. 65, since the insulating layer portion where the inspection pad does not exist is mechanically weaker than the new inspection pad, the crack CRK is generated by avoiding the inspection pad and the insulating layer portion. There was a problem of cutting and a problem that the cutting line was not fixed in the insulating layer portion between the pads for inspection of the dicing area and meandered. In particular, when the low-k film that is fragile and easily peeled off is used for the insulating layer, there is a problem that even if the bending method is used, a shape defect occurs in a divided portion of the low-k film, and it cannot be cut cleanly.

  Further, the technique disclosed in Patent Document 1 has a problem that it cannot be cut well because a wiring layer made of a metal having a higher strength than the insulating layer is formed on the cutting line between the chips. In addition, since a wiring layer is formed beside the test pad in order to make it easier to absorb the laser beam, the interval between adjacent chips must be widened accordingly, and the semiconductor chip that can be arranged in the plane of the semiconductor wafer There is a problem of reducing the number of.

  An object of the present invention is to provide a technique capable of reducing or preventing cutting shape defects in a semiconductor wafer cutting process using stealth dicing.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The present invention forms a modified region serving as a division starting point at the laser irradiation position inside the semiconductor wafer by irradiating a laser to the side of the inspection pad in the separation region of each semiconductor chip of the semiconductor wafer, The method includes a step of dividing individual semiconductor chips of the semiconductor wafer into pieces by a bending method.

  The present invention also provides a method for dividing the inspection pad in the semiconductor wafer cutting step by irradiating the inspection pad of the separation region of each semiconductor chip of the semiconductor wafer with a laser. And a step of forming a groove or a hole.

  According to another aspect of the present invention, there is provided a step of forming a modified region serving as a division starting point at a laser irradiation position inside the semiconductor wafer by irradiating a separation region of each semiconductor chip of the semiconductor wafer with a laser; And a step of removing the inspection pad.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  That is, after forming a modified region serving as a division starting point at a laser irradiation position inside the semiconductor wafer by irradiating a laser to the side of an inspection pad in a separation region of individual semiconductor chips of the semiconductor wafer, the semiconductor By dividing individual semiconductor chips of the wafer into pieces by a bending method, it is possible to reduce or prevent cutting shape defects in the cutting process of the semiconductor wafer using stealth dicing.

It is a flowchart of the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 2 is an overall plan view of a main surface of a semiconductor wafer after a pre-process 100 in FIG. 1. It is sectional drawing of the X1-X1 line | wire of FIG. FIG. 3 is an enlarged plan view of a main part of the semiconductor wafer in FIG. 2. FIG. 5 is an enlarged plan view of a region R1 in FIG. It is sectional drawing of the X2-X2 line | wire of FIG. It is principal part sectional drawing of the semiconductor wafer which showed the detailed example of the cross-section of the semiconductor wafer of FIG. It is a whole top view of the jig | tool in which the semiconductor wafer was accommodated. It is sectional drawing of the X3-X3 line | wire of FIG. It is sectional drawing of the semiconductor wafer and jig | tool at the time of a back surface process. It is sectional drawing of the semiconductor wafer and jig | tool after a back surface process. It is a principal part top view of the semiconductor wafer after a laser irradiation process. It is sectional drawing of the X4-X4 line | wire of FIG. It is a principal part top view of the other example of the semiconductor wafer after a laser irradiation process. It is a principal part top view of the further another example of the semiconductor wafer after a laser irradiation process. It is principal part sectional drawing of the semiconductor wafer before a division process. It is principal part sectional drawing of the semiconductor wafer at the time of a division | segmentation process. FIG. 18 is an enlarged cross-sectional view of a main part of the semiconductor wafer of FIG. 17. It is principal part sectional drawing of the semiconductor wafer in a division | segmentation process. It is the whole semiconductor chip top view cut out from a semiconductor wafer. It is a top view of the semiconductor chip and wiring board after a die-bonding process. It is sectional drawing of the X5-X5 line | wire of FIG. It is a top view of the semiconductor chip and wiring board after a wire bonding process. It is sectional drawing of the X6-X6 line | wire of FIG. It is sectional drawing of the semiconductor device after a sealing process. It is the whole semiconductor chip top view of the semiconductor device which is other embodiments of the present invention. FIG. 27 is a plan view of a mounting example of the semiconductor chip of FIG. 26. It is a principal part top view of the semiconductor wafer in the manufacturing process of the semiconductor device which is other embodiment of this invention. It is sectional drawing of the X8-X8 line | wire of FIG. It is sectional drawing of the X9-X9 line | wire of FIG. It is sectional drawing corresponding to the X8-X8 line | wire of FIG. 28 of the semiconductor wafer which shows a mode that the 1st time laser beam is irradiated. It is sectional drawing corresponding to the X9-X9 line | wire of FIG. 28 of the semiconductor wafer which shows a mode that the 1st laser beam is irradiated. It is a principal part top view of the semiconductor wafer after the irradiation process of the 1st laser beam. It is sectional drawing of the X10-X10 line | wire of FIG. It is sectional drawing of the X11-X11 line | wire of FIG. It is sectional drawing corresponding to the X8-X8 line | wire of FIG. 28 of the semiconductor wafer which shows a mode that the 2nd time laser beam is irradiated. It is sectional drawing corresponding to the X9-X9 line | wire of FIG. 28 of the semiconductor wafer which shows a mode that the 2nd time laser beam is irradiated. It is the whole semiconductor chip top view cut out from a semiconductor wafer. It is sectional drawing of the X12-X12 line | wire of FIG. It is a flowchart which shows the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 41 is a cross-sectional view of the semiconductor wafer after the WSS mounting process of FIG. 40. FIG. 41 is a cross-sectional view of the semiconductor wafer after the back grinding and polishing steps of FIG. 40. 41 is a fragmentary cross-sectional view of the semiconductor wafer during the laser irradiation step of FIG. 40. FIG. FIG. 41 is a plan view of the semiconductor wafer and jig after the wafer mounting step and the WSS peeling step of FIG. 40. It is sectional drawing of the X13-X13 line | wire of FIG. FIG. 41 is a main-portion cross-sectional view of the semiconductor wafer during the TEG processing step of FIG. 40; FIG. 41 is a main-portion cross-sectional view of the semiconductor wafer after the TEG processing step of FIG. 40; FIG. 41 is an essential part enlarged cross-sectional view of the semiconductor wafer during the dividing step of FIG. 40; FIG. 41 is an overall plan view of a semiconductor chip cut out from a semiconductor wafer by the dividing step of FIG. 40. It is sectional drawing of the X14-X14 line | wire of FIG. It is principal part sectional drawing of the semiconductor wafer in the laser irradiation process in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 52 is a main-portion cross-sectional view of the semiconductor wafer during the TEG processing step after FIG. 51; It is a principal part top view of the semiconductor wafer after a TEG processing process. It is sectional drawing of the X15-X15 line | wire of FIG. FIG. 54 is an essential part enlarged cross-sectional view of the semiconductor wafer during the dividing step after FIG. 53; FIG. 56 is an overall plan view of a semiconductor chip cut out from a semiconductor wafer by the dividing step of FIG. 55. It is sectional drawing of the X16-X16 line | wire of FIG. It is principal part sectional drawing of the semiconductor wafer in the TEG processing process of the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 59 is a main-portion cross-sectional view of the semiconductor wafer after the TEG processing step of FIG. 58; FIG. 60 is an essential part enlarged cross-sectional view of a semiconductor wafer during a division step subsequent to FIG. 59; It is principal part sectional drawing of the semiconductor wafer in the TEG processing process of the manufacturing process of the semiconductor device which is further another embodiment of this invention. FIG. 62 is an essential part enlarged cross-sectional view of the semiconductor wafer during the subsequent dividing step of FIG. 61; FIG. 63 is an enlarged cross-sectional view of the main part of the semiconductor wafer during the TEG processing step. It is sectional drawing of the semiconductor chip and wiring board which show the modification of FIG. It is principal part sectional drawing which shows the mode of the direction which a crack progresses when dividing | segmenting a semiconductor wafer. It is explanatory drawing of the subject produced by removing TEG using a dicing saw, after forming a crushing layer in a semiconductor wafer by laser irradiation. It is principal part sectional drawing of the semiconductor wafer in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 68 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 67; FIG. 69 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 68; FIG. 70 is a fragmentary cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 69; FIG. 71 is an overall cross sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 70; FIG. 72 is an overall cross-sectional view of the semiconductor wafer during a manufacturing step of the semiconductor device following that of FIG. 71; It is explanatory drawing of the subject which arises by irradiating a laser from the main surface side of a semiconductor wafer, after removing TEG using a dicing saw. It is a top view of the semiconductor wafer which is other embodiment of this invention. FIG. 75 is an enlarged plan view of a main part of the semiconductor wafer of FIG. 74. FIG. 76 is an essential part cross-sectional view of the semiconductor wafer of FIG. 75 when removing TEG; It is a top view which shows the mode of the division | segmentation of the semiconductor wafer which is other embodiment of this invention. (A) is the whole semiconductor wafer top view which showed the specific mode of the division | segmentation process of the semiconductor wafer demonstrated in FIG. 77, (b) is sectional drawing of the X17-X17 line | wire of (a). (A) And (b) is a principal part expanded sectional view of the semiconductor wafer at the time of a division | segmentation process. (A)-(c) is sectional drawing of the semiconductor wafer in the manufacturing process of the semiconductor device which is other embodiment of this invention.

  In the following embodiments, when it is necessary for the sake of convenience, the description will be divided into a plurality of sections or embodiments. However, unless otherwise specified, they are not irrelevant to each other. There are some or all of the modifications, details, supplementary explanations, and the like. Further, in the following embodiments, when referring to the number of elements (including the number, numerical value, quantity, range, etc.), especially when clearly indicated and when clearly limited to a specific number in principle, etc. Except, it is not limited to the specific number, and may be more or less than the specific number. Further, in the following embodiments, the constituent elements (including element steps and the like) are not necessarily indispensable unless otherwise specified and apparently essential in principle. Needless to say. Similarly, in the following embodiments, when referring to the shapes, positional relationships, etc. of the components, etc., the shapes are substantially the same unless otherwise specified, or otherwise apparent in principle. And the like are included. The same applies to the above numerical values and ranges. Also, components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof is omitted as much as possible. Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
A method of manufacturing the semiconductor device according to the first embodiment will be described with reference to the flowchart of FIG.

  First, in the pre-process 100, a semiconductor wafer (hereinafter referred to as a wafer) having a main surface and a back surface that are opposite to each other along the thickness direction is prepared, and a plurality of wafers are formed on the main surface (device forming surface) of the wafer. A semiconductor chip (hereinafter referred to as a chip) is formed. This pre-process 100 is also called a wafer process or wafer fabrication, and is a process until a chip (integrated circuit (element or wiring)) is formed on the main surface of the wafer and an electrical test can be performed with a probe or the like. is there. The pre-process includes a film formation process, an impurity introduction (diffusion or ion implantation) process, a photolithography process, an etching process, a metallization process, a cleaning process, and an inspection process between the processes.

  2 is an overall plan view of the main surface of the wafer 1W after the previous process 100, FIG. 3 is a cross-sectional view taken along line X1-X1 of FIG. 2, FIG. 4 is an enlarged plan view of the main part of the wafer 1W in FIG. 4 is an enlarged plan view of a region R1 in FIG. 4, FIG. 6 is a cross-sectional view taken along line X2-X2 in FIG. 5, and FIG. 7 is a cross-sectional view of the main part of the wafer 1W showing a detailed example of the cross-sectional structure of the wafer 1W in FIG. is there. In addition, the code | symbol N of FIG. 2 has shown the notch.

  As shown in FIGS. 2 and 3, the wafer 1 </ b> W is made of, for example, a substantially planar semiconductor thin plate having a diameter of about 300 mm, and a plurality of planar rectangular chips 1 </ b> C are arranged in a matrix on the main surface, for example. Has been.

  Each chip 1C is formed with a memory circuit such as a flash memory. Further, as shown in FIGS. 4 and 5, a plurality of bonding pads (hereinafter, bonding pads are referred to as pads) 1LB are provided at one end in the longitudinal direction of each chip 1C along one side in the longitudinal direction of the chip 1C. Are arranged side by side. The pad 1LB is an external terminal for extracting an electrode of a memory circuit (integrated circuit) formed on the chip 1C to the outside of the chip 1C, and is electrically connected to an element for forming a memory circuit through a wiring. The integrated circuit formed on the chip 1C may be formed with a logic circuit such as a microprocessor in addition to the memory circuit.

  A cutting region (chip separation region) CR is disposed on the outer periphery of each chip 1C. As shown in FIG. 4 and FIG. 5, a test element group (TEG) pad 1LBt and an alignment target Am are arranged in the cutting region CR. The test pad 1LBt is formed in a planar square shape, for example, and the size thereof is, for example, about 50 μm × 50 μm. The pad 1LBt is an external terminal for leading the electrode of the TEG element to the outside of the chip 1C, and is electrically connected to the TEG element through a wiring. The element for TEG is an element used for measuring or testing the electrical characteristics of the element formed in the chip 1C. The alignment target Am is formed in, for example, a planar cross shape, but may be formed in an L shape or a dot shape in addition to the cross shape. The alignment target Am is a pattern used when aligning a manufacturing apparatus such as an exposure apparatus and the chip 1C of the wafer 1W.

  A semiconductor substrate (hereinafter referred to as a substrate) 1S constituting such a wafer 1W is made of, for example, silicon (Si) single crystal, and an element and a wiring layer 1L are formed on its main surface. The thickness of the wafer 1W at this stage (the sum of the thickness of the substrate 1S and the thickness of the wiring layer 1L) D1 (see FIG. 3) is, for example, about 775 μm.

  As shown in FIGS. 6 and 7, the wiring layer 1L includes an interlayer insulating film 1Li, wiring, a pad (external terminal) 1LB, a test pad 1LBt, an alignment target Am, and a surface protective film (hereinafter referred to as a protective film). ) 1Lp is formed. The interlayer insulating film 1Li has a plurality of interlayer insulating films 1Li1, 1Li2, 1Li3.

Insulating films 2a and 2b are formed on the interlayer insulating film 1Li1. The insulating films 2a and 2b are alternately deposited on the substrate 1S. The insulating film 2a is formed of an inorganic insulating film such as silicon oxide (SiO ₂ or the like). The insulating film 2b is formed of an insulating film such as silicon nitride (Si ₃ N ₄ or the like), for example. The insulating film 2b is thinner than the insulating film 2a and functions as, for example, an etching stopper. In the interlayer insulating film 1Li1, plugs (contact plugs) PL1 and PL2 and a wiring L1 are formed.

  Plugs PL1 and PL2 are formed by embedding a conductor film in the holes H1 and H2. The conductor film forming the plugs PL1 and PL2 has a main conductor film and a barrier metal film formed so as to cover the outer peripheral surface (bottom surface and side surface) thereof. The main conductor film is made of tungsten (W), for example, and is thicker than the barrier metal film. The barrier metal film is made of, for example, titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), tantalum (Ta), titanium (Ti), tungsten (W), titanium tungsten (TiW), or a laminated film thereof. Is formed. The wiring L1 is, for example, a buried wiring. That is, the wiring L1 is formed by embedding a conductor film in the wiring trench T1 formed in the insulating films 2a and 2b. The configuration of the conductor film of the wiring L1 is the same as that of the plugs PL1 and PL2.

  In the interlayer insulating film 1Li2, insulating films 3a, 3b, 3c, 3d and wirings L2, L3 are formed. The insulating film 3a is made of, for example, silicon carbide (SiC) and has a function as an etching stopper. The insulating film 3a is formed thinner than the insulating films 3b, 3c, 3d.

  The insulating film 3b has a low dielectric constant whose dielectric constant is lower than that of silicon oxide (for example, 3.9 to 4.0) such as organic polymer or organic silica glass from the viewpoint of improving the operation speed of the semiconductor device. It is formed of a rate film (Low-k film). The insulating film 3b is formed thicker than the insulating films 3a, 3c, 3d.

  Examples of the organic polymer (fully organic low dielectric interlayer insulating film) include SiLK (manufactured by The Dow Chemical Co., USA, relative dielectric constant = 2.7, heat resistance temperature = 490 ° C. or higher, dielectric breakdown voltage = 4.0 to 4.0). 5.0 MV / Vm) or FLARE of polyallyl ether (PAE) material (manufactured by Honeywell Electronic Materials, relative permittivity = 2.8, heat-resistant temperature = 400 ° C. or higher). This PAE material is characterized by high basic performance and excellent mechanical strength, thermal stability and low cost.

  Examples of the organic silica glass (SiOC-based material) include HSG-R7 (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.8, heat-resistant temperature = 650 ° C.), Black Diamond (manufactured by Applied Materials, Inc., relative dielectric constant). = 3.0-2.4, heat-resistant temperature = 450 ° C.) or p-MTES (manufactured by Hitachi Development Co., Ltd., relative dielectric constant = 3.2). Examples of other SiOC-based materials include CORAL (manufactured by Novellus Systems, Inc., relative dielectric constant = 2.7 to 2.4, heat-resistant temperature = 500 ° C.), Aurora 2.7 (manufactured by Japan ASM Co., Ltd.). , Relative dielectric constant = 2.7, heat-resistant temperature = 450 ° C.).

  Other low dielectric constant film materials include, for example, fully organic SiOF materials such as FSG, HSQ (hydrogen silsesquioxane) materials, MSQ (methyl silsesquioxane) materials, porous HSQ materials, and porous MSQ materials. Alternatively, a porous organic material can be used.

  Examples of the HSQ-based material include OCD T-12 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 3.4 to 2.9, heat-resistant temperature = 450 ° C.), FOx (manufactured by Dow Corning Corp., USA), dielectric constant = 2.9) or OCL T-32 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative permittivity = 2.5, heat-resistant temperature = 450 ° C.).

  Examples of the MSQ material include OCD T-9 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.7, heat-resistant temperature = 600 ° C.), LKD-T200 (manufactured by JSR, relative dielectric constant = 2.7-2. 5, heat-resistant temperature = 450 ° C., HOSP (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.5, heat-resistant temperature = 550 ° C.), HSG-RZ25 (manufactured by Hitachi Chemical, relative dielectric constant = 2.5, heat-resistant Temperature = 650 ° C.), OCL T-31 (manufactured by Tokyo Ohka Kogyo Co., Ltd., dielectric constant = 2.3, heat-resistant temperature = 500 ° C.) or LKD-T400 (manufactured by JSR, dielectric constant = 2.2-2, heat-resistant temperature) = 450 ° C.).

  Examples of the porous HSQ material include XLK (manufactured by Dow Corning Corp., relative dielectric constant = 2.5-2), OCL T-72 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2-1.9). , Heat resistant temperature = 450 ° C), Nanoglass (manufactured by Honeywell Electronic Materials, relative dielectric constant = 2.2 to 1.8, heat resistant temperature = 500 ° C or higher) or MesoELK (US Air Products and Chemicals, Inc, relative dielectric constant = 2) Etc.)

  Examples of the porous MSQ material include HSG-6221X (manufactured by Hitachi Chemical Co., Ltd., relative dielectric constant = 2.4, heat-resistant temperature = 650 ° C.), ALCAP-S (manufactured by Asahi Kasei Kogyo Co., Ltd., relative dielectric constant = 2.3-1). .8, heat resistant temperature = 450 ° C.), OCL T-77 (manufactured by Tokyo Ohka Kogyo Co., Ltd., relative dielectric constant = 2.2 to 1.9, heat resistant temperature = 600 ° C.), HSG-6210X (manufactured by Hitachi Chemical Co., Ltd., dielectric constant) Rate = 2.1, heat-resistant temperature = 650 ° C.) or silica aerogel (manufactured by Kobe Steel, relative dielectric constant: 1.4 to 1.1).

  Examples of the porous organic material include PolyELK (US Air Products and Chemicals, Inc., dielectric constant = 2 or less, heat-resistant temperature = 490 ° C.), and the like.

The SiOC material and the SiOF material are formed by, for example, a CVD method (Chemical Vapor Deposition). For example, the Black Diamond is formed by a CVD method using a mixed gas of trimethylsilane and oxygen. The p-MTES is formed by, for example, a CVD method using a mixed gas of methyltriethoxysilane and N ₂ O. The other low dielectric constant insulating materials are formed by, for example, a coating method.

The insulating film 3c is made of, for example, silicon oxide. The insulating film 3c has functions such as ensuring the mechanical strength, surface protection, and moisture resistance of the low dielectric constant film during, for example, chemical mechanical polishing (CMP). The insulating film 3c is formed with substantially the same thickness as the insulating film 3d. The material of the insulating film 3c is not limited to the silicon oxide film described above and can be variously changed. For example, a silicon nitride (Si _x N _y ) film, a silicon carbide film, or a silicon carbonitride (SiCN) film is used. Also good. These silicon nitride film, silicon carbide film, or silicon carbonitride film can be formed by, for example, a plasma CVD method. As a silicon carbide film formed by the plasma CVD method, for example, there is BLOk (manufactured by AMAT, relative permittivity = 4.3).

  The insulating film 3d is made of, for example, silicon carbonitride. In addition to the function as an etching stopper, the insulating film 3d has a function of suppressing or preventing the diffusion of copper forming the main conductor film of the wirings L2 and L3.

  The wirings L2 and L3 are the embedded wirings. That is, the wirings L2, L3 are formed by embedding a conductor film in the wiring trenches T2, T3. Similar to the wiring L3, the conductor film of the wirings L2 and L3 includes a main conductive film and a barrier metal film formed so as to cover the outer peripheral surface (bottom surface and side surfaces) thereof. The main conductor film is made of, for example, copper (Cu) and is thicker than the barrier metal film. The material of the barrier metal film is the same as that of the plugs PL1 and PL2. The wiring L3 is electrically connected to the wiring L2 through the hole H3. The conductor film of the wiring groove T3 of the wiring L3 and the conductor film of the hole H3 are integrally formed.

  The interlayer insulating film 1Li3 is made of, for example, silicon oxide. A plug PL3 is formed in the interlayer insulating film 1Li3. The plug PL3 is formed by embedding a conductor film in the hole H4. The conductor film forming the plug PL3 is the same as the plugs PL1 and PL2.

  On the interlayer insulating film 1Li3, wirings, the pads 1LB and 1LBt, and the alignment target Am are formed. The wiring, pads 1LB, 1LBt, and alignment target Am are formed of a metal film such as aluminum. Such uppermost wiring and pads 1LB, 1LBt, etc. are covered with a protective film 1Lp formed on the uppermost layer of the wiring layer 1L. The protective film 1Lp includes, for example, an inorganic insulating film 1Lp1 such as silicon oxide, an inorganic insulating film 1Lp2 deposited thereon, for example, silicon nitride, and further deposited thereon, such as polyimide It is formed of a laminated film with an organic insulating film 1Lp3 such as resin. An opening 5 is formed in a part of the protective film 1Lp, and parts of the pads 1LB and 1LBt are exposed therefrom.

  In the first embodiment, the test pad 1LBt (including TEG elements and wiring) and the alignment target Am are arranged close to one side in the width direction (short direction) of the cutting region CR. . That is, the test pad 1LBt and the alignment target Am are arranged so as to be shifted from the center in the width direction of the cutting region CR. Then, the cutting line CL to which the laser beam is irradiated at the time of stealth dicing does not pass on the placement line of the test pad 1LBt and the alignment target Am, but passes by the side of the test pad 1LBt and the alignment target Am. It has become. That is, the cutting line CL passes through a position away from the test pad 1LBt and the alignment target Am without straddling the test pad 1LBt and the alignment target Am.

  When the cutting line CL overlaps a metal pattern such as the test pad 1LBt or the alignment target Am, the mechanical strength varies depending on whether or not the metal pattern is present, and the low dielectric constant film is fragile. It cannot be divided neatly because it is easily peeled off from the metal pattern. Further, when the cutting line CL overlaps a metal pattern such as the pad 1LBt or the alignment target Am, a whisker-like conductor foreign matter is left in the cut portion of the metal pattern at the time of cutting, and the conductor foreign matter is bonded to a bonding wire, an electrode, or the like. There is a problem that a short-circuit failure is caused by contact with the substrate, and the reliability and yield of a thin semiconductor device are lowered.

  On the other hand, in the first embodiment, since the cutting line CL does not overlap the test pad 1LBt or the alignment target Am, the wafer 1W can be cut cleanly. In addition, since the metal patterns such as the test pad 1LBt and the alignment target Am are not cut, generation of the above-described whisker-like conductor foreign matters can be prevented. Therefore, the reliability and yield of a thin semiconductor device can be improved.

  Further, when the cutting line CL overlaps a metal pattern such as the test pad 1LBt and the alignment target Am, when the laser light is irradiated from the main surface side of the wafer 1W during the stealth dicing process, the pad 1LBt, the alignment target Am, etc. This makes it difficult to form a modified region on the substrate 1S. On the other hand, in the first embodiment, the cutting line CL does not overlap the test pad 1LBt or the alignment target Am, so that the substrate 1S is good even when the laser beam is irradiated from the main surface of the wafer 1W during the stealth dicing process. A modified region described later can be formed. Therefore, the degree of freedom of laser irradiation can be improved.

  Next, in the test process 101 of FIG. 1, various electrical characteristic inspections are performed by applying probes to the pads 1LB of each chip 1C of the wafer 1W and the test pads 1LBt of the cutting region CR. This test process is also referred to as a G / W (Good chip / Wafer) check process, and is a test process that mainly electrically determines the quality of each chip 1C formed on the wafer 1W.

  A subsequent process 102 in FIG. 1 is a process until the chip 1C is housed in a sealing body (package) and completed, and includes a back surface processing process 102A, a chip dividing process 102B, and an assembling process 102C. Hereinafter, the back surface processing step 102A, the chip dividing step 102B, and the assembly step 102C will be described in order.

  The back surface processing step 102A is a step of thinning the wafer 1W. First, in the back surface processing step, the wafer 1W is accommodated in a jig. 8 is an overall plan view of the jig 7 in which the wafer 1W is accommodated, and FIG. 9 is a sectional view taken along line X3-X3 of FIG. In FIG. 8, the chip 1C on the main surface of the wafer 1W is indicated by a broken line.

  The jig 7 has a tape 7a and a ring (frame body) 7b. The tape base 7a1 of the tape 7a is made of, for example, a flexible plastic material, and an adhesive layer 7a2 is formed on the main surface thereof. The tape 7a is firmly attached to the main surface (chip forming surface) of the wafer 1W by the adhesive layer 7a2. If the thickness of the tape 7a (the sum of the thickness of the tape base 7a1 and the thickness of the adhesive layer 7a2) is too thick, handling in the subsequent steps and peeling of the tape 7a become difficult. For example, the tape 7a is as thin as about 130 to 210 μm. Is used. As this tape 7a, it is also preferable to use, for example, a UV tape. The UV tape is an adhesive tape in which an ultraviolet (UV) curable resin is used as a material of the adhesive layer 7a2, and has a property that the adhesive force of the adhesive layer 7a2 is rapidly weakened when irradiated with ultraviolet rays while having a strong adhesive force. (Step 102A1).

  In the first embodiment, a rigid ring 7b is affixed to the outer periphery of the main surface (the affixing surface of the wafer 1W) of the tape 7a. The ring 7b is a reinforcing member having a function of supporting the tape 7a so as not to bend. From the viewpoint of reinforcement, the ring 7b is preferably formed of a metal such as stainless steel, but may be formed of a plastic material whose thickness is set so as to have the same degree of hardness as the metal. Notches 7b1 and 7b2 are formed on the outer periphery of the ring 7b. The notches 7b1 and 7b2 are used as hooks when the jig 7 is fixed to the manufacturing apparatus, as well as when the jig 7 is handled and when the jig 7 is aligned with the manufacturing apparatus on which the jig 7 is placed. used. The ring 7b may be affixed to the back surface of the tape 7a (the surface opposite to the affixing surface of the wafer 1W). The ring 7b may be attached before the wafer 1W is attached to the tape 37, or may be attached after the wafer 1W is attached to the tape 7a.

  Subsequently, after the wafer 1W is housed in the jig 7, the thickness of the wafer 1W is measured, and after calculating the grinding amount and the polishing amount based on the measurement result (step 102A2), the back surface grinding (step 102A3) Then, the process proceeds to the polishing step (step 102A4). 10 is a cross-sectional view of the wafer 1W and the jig 7 during the back surface processing step, and FIG. 11 is a cross-sectional view of the wafer 1W and the jig 7 after the back surface processing step. Here, as shown in FIG. 10, the grinding / polishing tool 8 and the suction stage 9 are rotated, and the grinding process and the polishing process are sequentially performed on the back surface of the wafer 1W based on the grinding amount and the polishing amount. As a result, as shown in FIG. 11, the thickness of the wafer 1W is set to an extremely thin thickness (ultra thin), for example, 100 μm or less (here, for example, about 90 μm). As the polishing treatment, for example, an etching method using nitric acid and hydrofluoric acid may be used in addition to a polishing method using a polishing pad and silica or a chemical mechanical polishing (CMP) method. Here, when the thickness of the chip 1C is reduced to 100 μm or less, the bending strength of the chip is lowered due to damage or stress generated on the back surface of the wafer 1W by the grinding process, and the chip 1C is mounted. The problem that the chip breaks due to pressure is likely to occur. Therefore, by performing the polishing process after the grinding process, it is possible to reduce or eliminate the damage and stress generated on the back surface of the wafer 1W by the grinding process, so that the bending strength of the thin chip 1C can be improved.

  After the back surface processing step as described above, the vacuum suction state of the suction stage 9 is released, and the jig 7 holding the wafer 1W is taken out from the back surface processing apparatus. At this time, in the first embodiment, since the tape 7a can be firmly supported by the ring 7b even if the wafer 1W is extremely thin, handling and conveyance of the extremely thin wafer 1W can be facilitated. . Further, it is possible to prevent the wafer 1W from being cracked or warped during the handling or transfer. Therefore, the quality of the wafer 1W can be ensured. For this reason, in the first embodiment, the ultrathin wafer 1W is held by the jig 7 at the stage after the back surface processing, and is transported and shipped to another manufacturing factory (for example, an assembly fab). Dicing and assembly after processing may be requested.

  Next, the process proceeds to the chip dividing step 102B. Here, first, the jig 7 holding the ultra-thin wafer 1 </ b> W is directly transferred to the dicing apparatus and placed on the suction stage of the dicing apparatus. That is, usually, a process of peeling off the tape attached to the main surface of the wafer 1W during back surface processing and attaching a dicing tape to the back surface of the wafer 1W (wafer mounting) is required. Then, since the wafer mounting process can be reduced, the manufacturing process of the semiconductor device can be simplified. Therefore, the manufacturing time of the semiconductor device can be shortened. In addition, since the dicing tape can be omitted, the material cost can be reduced and the cost of the semiconductor device can be reduced.

  Subsequently, in the first embodiment, the pattern of the main surface of the wafer 1W (the pattern of the chip 1C and the cutting region CR) from the back surface of the wafer 1W with an infrared camera (hereinafter referred to as IR camera) in a state where the jig 7 is vacuum-sucked. In addition, a metal pattern such as the pad 1LBt and the alignment target Am arranged in the cutting region CR and a metal pattern such as the pad 1LB arranged in the chip 1C are recognized (step 102B1). At this time, in the first embodiment, since the wafer 1W is extremely thin, the pattern of the main surface of the wafer 1W can be sufficiently observed.

  Then, after alignment (position correction) of the cutting line CL is performed based on the pattern information obtained by the IR camera, the laser beam (first laser) LB1 emitted from the laser generator is used as the back side of the wafer 1W. To the inside of the substrate 1S in a state where the condensing point (focal point) is aligned, and is moved along the cutting line CL aligned based on the pattern information (step 102B2). FIG. 12 is a plan view of the main part of the wafer 1W after the laser irradiation step, and FIG. 13 is a cross-sectional view taken along line X4-X4 of FIG. By the laser irradiation process, a modified region (an optically damaged portion or a fractured layer) PR by multiphoton absorption is formed inside the substrate 1S in the cutting region CR of the wafer 1W. FIG. 12 illustrates a case where the modified region PR is continuously formed along the cutting line CL by continuously irradiating the laser beam LB1 along the cutting region CR. Yes.

  This modified region PR is formed by heating and melting the inside of the wafer 1W by multiphoton absorption, and becomes a cutting start region of the wafer 1W in the subsequent chip dividing step. This melting treatment region is a region that has been once melted and then re-solidified, a region that is in a molten state, a region that is re-solidified from a molten state, and can also be referred to as a phase-changed region or a region in which the crystal structure has changed. . The melt treatment region can also be said to be a region in which one structure is changed to another structure in a single crystal structure, an amorphous structure, or a polycrystalline structure. For example, in the substrate 1S portion, a region changed from a single crystal structure to an amorphous structure, a region changed from a single crystal structure to a polycrystalline structure, and a region changed from a single crystal structure to a structure including an amorphous structure and a polycrystalline structure Means. Here, the modified layer PR is made of, for example, amorphous silicon. In addition, here, the laser beam LB1 is transmitted through the back surface of the wafer 1W to generate multiphoton absorption inside the wafer 1W to form the modified region PR, and the laser beam LB1 is almost absorbed on the back surface of the wafer 1W. Since this is not done, the back surface of the wafer 1W does not melt.

  Here, when the laser beam LB1 is irradiated as described above, in the first embodiment, the laser beam LB1 is irradiated to the side of the test pad 1LBt in the cutting region CR. That is, the laser beam LB1 is irradiated so as not to overlap the pad 1LBt and the alignment target Am in a plane. That is, the division starting point (modified region PR) of the wafer 1W is prevented from overlapping the pad 1LBt and the alignment target Am in a plane. Thereby, when the wafer 1W is cut, the metal pattern such as the test pad 1LBt and the alignment target Am is not cut, so that the wafer 1W can be cut cleanly. That is, it is possible to reduce or prevent a defective cutting shape of the wafer 1W. In addition, it is possible to prevent the above-described whisker-like conductor foreign matter from being generated at the cut portion. Therefore, the reliability and yield of a thin semiconductor device can be improved.

  Further, in the case of the blade dicing method in which the wafer 1W is cut by a dicing blade, chipping tends to occur at the time of cutting when the wafer 1W becomes thin, and the bending strength of the chip is lowered. From the viewpoint of ensuring the quality of the chip 1C. Processing must be performed at low speed (for example, about 60 mm per second or less depending on the thickness of the wafer 1W). On the other hand, in the case of the first embodiment, since only the inside is cleaved without damaging the surface of the wafer 1W, chipping existing on the surface of the chip 1C can be minimized. For this reason, the bending strength of the chip 1 </ b> C can be improved. Further, for example, a high-speed cutting process of 300 mm per second can be performed, so that the throughput can be improved.

  Further, as described above, when the laser beam LB1 is irradiated from the main surface side of the wafer 1W to the cutting region CR of the main surface of the wafer 1W, the test pad 1LBt becomes a hindrance and the portion is processed (the modified region PR). Formation) may not be successful. On the other hand, in the first embodiment, the laser beam LB1 is irradiated from the back side of the wafer 1W where no metal such as the test pad 1LBt is present. The modified region PR can be formed, and the wafer 1W can be cut well.

  The modified region PR may be formed in a broken line shape (dot shape) as shown in FIGS. 14 and 15. FIG. 14 illustrates a case where the modified region PR is arranged in a broken line shape (dot shape) along the cutting line CL. That is, the reformed regions PR are arranged at regular intervals along the cutting line CL. The low dielectric constant film (insulating film 3b) used for the interlayer insulating film 1Li has a low thermal conductivity and is likely to trap heat, so that it may be discolored by heat during irradiation with the laser beam LB1. Therefore, by intermittently irradiating the laser beam LB1, the irradiation area of the laser beam LB1 can be reduced, and the generation of heat due to the irradiation of the laser beam LB1 can be suppressed as much as possible. It can be suppressed or prevented. Further, FIG. 15 shows that the modified region PR is concentratedly arranged at a location that is difficult to divide, such as an intersection of cutting lines CL orthogonal to each other or a location where fine patterns of TEG are concentrated. The case of being is illustrated. As a result, since it is possible to easily divide a portion that is difficult to divide, the wafer 1W can be neatly divided. 14 and 15 is the same as that of FIG. Moreover, although it does not specifically limit, the irradiation conditions of the laser beam LB1 are as follows, for example. That is, the light source was, for example, a YAG laser having a wavelength of 1064 nm, the laser spot diameter was, for example, 1-2 μm, the irradiation speed was 300 mm / s, and irradiation was performed at 0.7 μm intervals. In addition, the said condensing point is a location which the laser beam LB1 condensed.

  Next, the process proceeds to the wafer 1W dividing step (step 102B3). 16 is a fragmentary sectional view of the wafer 1W before the dividing step, FIG. 17 is a fragmentary sectional view of the wafer 1W during the dividing step, FIG. 18 is an enlarged sectional view of the principal portion of the wafer 1W in FIG. The principal part sectional drawing of wafer 1W in the inside is shown.

  First, as shown in FIG. 16, the IR camera 12 is used to pattern the main surface of the wafer 1W (such as the pattern of the chip 1C and the cutting area CR, as well as the pads 1LBt and the alignment target Am arranged in the cutting area CR). A metal pattern or a metal pattern such as a pad 1LB arranged in the chip 1C) or a modified region PR.

  Subsequently, a pair of line vacuum chucks 13 are arranged on the back surface of the tape 7a of the jig 7, and the positions of the line vacuum chucks 13 are adjusted based on the position information obtained by the IR camera 12, and in this state, The tape 7 a is sucked by the line vacuum chuck 13. The pair of line vacuum chucks 13 extends from the end of the wafer 1 </ b> W to the end (direction perpendicular to the paper surface). A slope is formed on one of the opposing side surfaces of the pair of line vacuum chucks 13.

  Thereafter, as shown in FIGS. 17 and 18, one line vacuum chuck 13 (left side in FIGS. 17 and 18) is rotated until its side surface (inclined surface) hits the opposite side surface of the other line vacuum chuck 13. The wafer 1W is bent by moving as described above. As a result, the wafer 1W is cut (divided) using the modified region PR as a division starting point. Thereafter, as shown in FIG. 19, after the one line vacuum chuck 13 is returned to the original position, the pair of line vacuum chucks 13 are moved to the next cutting position. Thereafter, the wafer 1W is cut in the same manner as described above. Thereafter, such an operation is repeated until all the chips 1C on the wafer 1W are cut. In the first embodiment, the cutting line CL does not overlap the test pad 1LBt or the alignment target Am. As a result, even if the expanding method is adopted as the dividing method, the metal patterns such as the test pad 1LBt and the alignment target Am are not cut, so that generation of the above-mentioned whisker-like conductor foreign matters can be prevented. However, as described above, in the case of the expand method, the resin sheet is stretched in the direction from the center of the wafer 1W toward the outer periphery (radially), and therefore the chip 1C intersects the cutting line CL (vertical direction). Not pulled apart. In other words, the load (stress) for cutting in the direction intersecting the cutting line CL is not transmitted. As a result, there is a possibility that the wafer 1W cannot be cut cleanly. In some cases, chipping may occur on the outer periphery of the chip. On the other hand, if the bending method is applied, it is possible to transmit the load for cutting in the direction intersecting the cutting line CL, and thus the wafer 1W can be cut cleanly.

  FIG. 20 is an overall plan view of the chip 1C cut out from the wafer 1W as described above. Here, a case where a plurality of pads 1LB are arranged along only one side of one end in the longitudinal direction of the chip 1C is illustrated. In the case of the first embodiment, a part of the cutting region CR is left on the outer periphery (two sides intersecting (orthogonal)) of the chip 1C, and the test pad 1LBt is left in the cutting region CR. In the first embodiment, after stealth dicing as described above, the jig 7 on which a plurality of ultra-thin chips 1C are placed is transported and shipped to another manufacturing factory (for example, an assembly fab), and after the dicing process. Assembly may be requested.

  Next, the process proceeds to the assembly process 102C. Here, the jig 7 holding the plurality of chips 1C is transported to the pickup device. In the pickup device, the chip 1C is pushed up from the back surface of the tape 7a by a push-up pin in a state where the back surface of the tape 7a is vacuum-sucked. At this time, when the UV tape is used as the tape 7a, the adhesive layer 7a2 of the tape 7a is irradiated with ultraviolet rays to cure the adhesive layer 7a2 and weaken the adhesive force. In this state, the chip 1C is picked up by vacuuming the chip 1C with a collet (step 102C1).

  Subsequently, after the chip 1C picked up as described above is inverted by an existing inversion unit so that the main surface of the chip 1C faces upward, the chip 1C is mounted on a wiring board or the like (die bonding step 102C2). 21 is a plan view of the chip 1C and the wiring board 15 after the die bonding process, and FIG. 22 is a cross-sectional view taken along line X5-X5 of FIG. On the main surface of the wiring board 15, for example, three chips 1 </ b> C are mounted in a state of being stacked with the main surface facing up. The three chips 1C are stacked in a state shifted in plan so that the pad 1LB of each chip 1C is exposed. The wiring board 15 is formed of a printed wiring board, but a lead frame may be used instead. Note that the picked-up chip 1C may be accommodated in a transport tray, transported and shipped to another manufacturing factory (for example, an assembly fab), and assembly after this process may be requested (process 103A).

  Subsequently, the process proceeds to a wire bonding process (process 102C3). 23 is a plan view of the chip 1C and the wiring board 15 after the wire bonding process, and FIG. 24 is a cross-sectional view taken along line X6-X6 of FIG. In this step, the pad 1LB on the main surface of the chip 1C and the electrode of the wiring board 15 are electrically connected by a bonding wire (hereinafter simply referred to as a wire) 17. Here, as shown in FIG. 64, the step bonding method in which the pad 1LB of the upper chip 1C and the pad 1LB of the lower chip 1C are electrically connected by the wire 17, that is, the common pads are electrically connected to each other. May be used.

  Then, it transfers to a sealing process (process 102C4). FIG. 25 shows a cross-sectional view of the semiconductor device after the sealing step. In this step, the chip 1C and the wire 17 are sealed by a sealing body 18 made of a plastic material such as an epoxy resin using a transfer mold method. Thereafter, bump electrodes 19 are formed on the back surface of the wiring substrate 15 to manufacture a semiconductor device.

  When the chip 1C has bump electrodes (projection electrodes), for example, the following is performed. First, in the pickup step 102C1, the chip 1C is transferred to the chip mounting area of the wiring board 15. At this time, the bump electrode can be mounted on the wiring board 15 without being tilted by connecting the bump electrode to the pad 1LB and the test pad 1LBt. Subsequently, the bump electrodes of the chip 1C and the electrodes in the chip mounting area are temporarily fixed using a paste material in a state where the main surface (bump electrode forming surface) of the chip 1C is directed to the chip mounting surface of the wiring board 15. Thereafter, the bump electrode of the chip 1C and the electrode of the printed wiring board 15 are fixed by reflow treatment (flip chip bonding: step 102C2). Thereafter, an underfill is filled between the opposing surfaces of the chip 1C and the wiring substrate 15, and then the chip 1C is sealed in the same manner as above (step 104C4).

(Embodiment 2)
In the second embodiment, a modified example of the arrangement of the pads 1LB in the chip 1C will be described. FIG. 26 is an overall plan view of the chip 1C of the second embodiment. In the present second embodiment, a plurality of pads 1LB are arranged along each of two sides that intersect (orthogonally) each other of the chip 1C. The rest is the same as in the first embodiment, and a part of the cutting region CR is left on the outer periphery (two sides intersecting (orthogonal)) of the chip 1C, and the test pad 1LBt is in the cutting region CR. It is left.

  FIG. 27 is a plan view of a mounting example of the chip 1C of FIG. The sectional view taken along line X7-X7 in FIG. 27 is the same as FIG. On the main surface of the wiring board 15, for example, three chips 1 </ b> C are mounted in a state of being stacked with the main surface facing up. The three chips 1C are stacked in a state shifted in a plane so that a plurality of pads 1LB arranged along two sides of each chip 1C are exposed.

(Embodiment 3)
First, the problems found by the inventor for the first time before the description of the third embodiment will be described. As described above, in the division of the wafer 1W, there is a problem that the whisker-like conductor foreign matter is generated in the cut portion of the metal pattern such as the test pad 1LBt and the alignment target Am existing in the cutting region CR. In order to avoid this problem, the present inventor has formed a perforated or linear groove in a metal pattern such as the pad 1LBt or the alignment target Am in the cutting region CR. However, when the expanding method is adopted as the dividing method, there is a problem that even if a perforated or linear groove is formed in the metal pattern, generation of whisker-like conductor foreign matter cannot be suppressed well. In addition, there is a problem that the cutting line meanders only at the portion of the insulating film between the adjacent metal patterns in the cutting region CR, and cannot be cut cleanly.

  Therefore, when a bending method in which the wafer 1W is bent and divided into individual chips 1C is adopted, the generation of the whisker-like conductive foreign matter can be reduced as compared with the expanding method. However, even in the case of the bending method, the cutting line meanders between the metal patterns. In particular, when a low dielectric constant film is used for the interlayer insulating film as described above, the low dielectric constant film is brittle and easily cracked, so that there is a crack that causes a large meander at the cut portion between adjacent metal patterns, There is a problem that it cannot be cut sufficiently cleanly. Here, the present inventor tried to form a groove for the division starting point by irradiating the interlayer insulating film portion between the adjacent metal patterns with a laser beam. In the third embodiment, such a problem is caused. Means for solving will be described. FIG. 28 is a plan view of the principal part of the wafer 1W according to the third embodiment, FIG. 29 is a sectional view taken along line X8-X8 in FIG. 28, and FIG. 30 is a sectional view taken along line X9-X9 in FIG.

  A wafer 1W shown in FIGS. 28 to 30 shows the wafer 1W after the pre-process 100 and the test process 101 in FIG. In the third embodiment, a metal pattern such as a test pad 1LBt and an alignment target Am is arranged on the cutting line CL in the cutting region CR. That is, the cutting line CL overlaps a metal pattern such as the test pad 1LBt and the alignment target Am. On the cutting line CL, a metal pattern 20 is formed so as to fill a gap between adjacent test pads 1LBt and a gap between the test pads 1LBt and the alignment target Am. However, the metal pattern 20 is not in contact with a metal pattern such as the test pad 1LBt or the alignment target Am, and is in an electrically floating state. The metal pattern 20 is formed of the same material in the same process as the test pad 1LBt and the alignment target Am. However, here, the width (dimension in the short direction) of the metal pattern 20 is smaller than the length of one side of the test pad 1LBt, for example, about 5 to 10 μm. Thereby, material cost can be reduced. A part of the upper surface of the metal pattern 20 is exposed through the opening 5 opened in the protective film 1Lp.

  Next, the back surface processing step 102A is performed on the wafer 1W in the same manner as in the first embodiment to reduce the thickness, and then the process proceeds to the chip division step 102B. In the chip dividing step, the wafer main surface pattern recognition step 102B1 is performed as in the first embodiment, and then the laser irradiation step 102B2 is performed. In Embodiment 3, laser light irradiation is performed twice.

  The first laser beam irradiation is for forming a division start point in the metal pattern of the cutting region CR. FIG. 31 and FIG. 32 are cross-sectional views of main parts of the wafer 1W showing a state in which the first laser beam LB2 is irradiated. 31 corresponds to the X8-X8 line of FIG. 28, and FIG. 32 corresponds to the X9-X9 line of FIG. In the first laser beam irradiation, the cutting line CL is aligned (position correction) based on the pattern information obtained by the IR camera, and then the laser beam LB2 emitted from the laser generator is used as the back surface of the wafer 1W. From the side, the test pad 1LBt, the alignment target Am, and the metal pattern 20 are irradiated with a focus, and moved along a cutting line that is aligned based on the pattern information. The cutting line according to the third embodiment is substantially in the center in the width direction (short direction) of the cutting region CR and overlaps the test pad 1LBt, the alignment target Am, and the metal pattern 20. The irradiation conditions of the laser beam LB2 are as follows, for example. That is, the light source was a YAG laser with a wavelength of 1064 nm, for example, and the irradiation speed was 300 mm / s.

  FIG. 33 is a plan view of an essential part of the wafer 1W after the laser beam LB2 irradiation step, and FIGS. 34 and 35 are cross-sectional views taken along lines X10-X10 and X11-X11 in FIG. By irradiating the laser beam LB2 as described above, the test pads 1LBt, the alignment target Am, and the metal pattern 20 are formed with a plurality of holes 21 in a plane perforation (broken line shape, dot shape) along the cutting line. To do. The holes 21 serve as a division starting point during the division (cutting) process of the wafer 1W. That is, in the third embodiment, the test pattern 1LBt adjacent to each other is provided by providing the metal pattern 20 between the test pads 1LBt adjacent to each other or between the test pad 1LBt and the alignment target Am. An array of a plurality of holes 21 serving as division starting points can also be formed between the test pad 1LBt and the alignment target Am. When the laser beam LB2 is irradiated, the molten foreign matter adheres to the test pad 1LBt and the like, so it is important that the tape 7a is in close contact with the unevenness of the cutting region CR from the viewpoint of suppressing or preventing the molten foreign matter from scattering. It is.

  The second laser beam irradiation is for forming the modified region PR described in the first embodiment. 36 and 37 are cross-sectional views of the main part of the wafer 1W showing a state in which the second laser beam LB1 is irradiated. 36 corresponds to the X8-X8 line in FIG. 28, and FIG. 37 corresponds to the X9-X9 line in FIG. Here, as in the first embodiment, the laser beam LB1 is irradiated from the back surface side of the wafer 1W while focusing on the inside of the substrate 1S. In this way, the modified region PR is formed in the substrate 1S. However, in the third embodiment, the laser beam LB1 is irradiated to the center in the width direction (short direction) of the cutting region CR. That is, the operation locus of the laser beam LB1 generator is the same as the operation locus of the laser beam LB2 generator. However, as described in the first embodiment, the planar shape of the modified region PR may be linearly formed in a planar manner or may be formed in a broken line shape. When the laser beams LB1 and LB2 are irradiated from the same back side of the wafer 1W, the laser beam LB1 is irradiated after the laser beam LB2 is irradiated. This is because if the laser beam LB1 is irradiated before the laser beam LB2, the modified region PR formed on the substrate 1S by the laser beam LB1 is obstructed when the laser beam LB2 is irradiated. This is because the holes 21 cannot be formed in the metal pattern in the region CR.

  Next, in the dividing step 102B3, the wafer 1W is divided (cut) by the bending method as in the first embodiment. 38 is an overall plan view of the chip 1C cut out from the wafer 1W, and FIG. 39 is a sectional view taken along line X12-X12 in FIG. In the case of the third embodiment, it is possible to cleanly cut the wafer 1W along the arrangement of the holes 21. That is, even in the case where a low dielectric constant film is used as the interlayer insulating film, there are a plurality of layers between the test pads 1LBt adjacent to each other and between the test pads 1LBt and the alignment target Am. The wafer 1 </ b> W can be divided (cut) without meandering along the array of the holes 21. Therefore, the defective cutting shape of the wafer 1W can be reduced or prevented, so that the yield and reliability of the semiconductor device can be improved. Note that a part of the test pad 1LBt, the alignment target Am, and the metal pattern 20 is left on the outer periphery of the chip 1C. Since the assembly process 102C is the same as that of the first embodiment, description thereof is omitted.

(Embodiment 4)
In the first to third embodiments, since the test pad 1LBt and the TEG element are left on the outer periphery of the chip 1C, there is a problem that TEG information leaks to the outside. In the fourth embodiment, means for avoiding such a problem will be described. Hereinafter, an example of a method for manufacturing the semiconductor device according to the fourth embodiment will be described with reference to FIGS.

  First, similarly to the first embodiment, after the pre-process 200 and the test process 201, the process proceeds to the post-process 202. In the back surface processing step 202A of the post-step 202, a support substrate is attached to the main surface of the wafer 1W via an adhesive layer (step 202A1). FIG. 41 shows a cross-sectional view of the wafer 1W after the support substrate 24 is mounted.

  The support substrate 24 is a wafer support system (WSS) that functions as a reinforcing member for the wafer 1 </ b> W in subsequent steps. As a result, when the wafer 1W is transported, the ultra-thin and large-diameter wafer 1W can be handled in a stable state, and the wafer 1W can be protected from external impacts. Can be suppressed or prevented. In each subsequent process, warping and bending of the wafer 1W can be suppressed or prevented, and the flatness of the ultra-thin and large-diameter wafer 1W can be improved, so that the processing stability in each process is improved. And controllability can be improved.

  As the material of the support substrate 24, for example, a hard support substrate (Hard-WSS or Glass-WSS) such as transparent glass is used. However, as another material of the support substrate 24, another hard support substrate (Hard-WSS) such as stainless steel may be used. Further, as another material of the support substrate 24, a tape WSS in which an insulating support substrate such as PET (Polyethylene Terephthalate) or PEN (Polyethylene Naphthalate) is attached to a tape base material may be used.

  When the support substrate 24 is attached to the main surface of the wafer 1W, the support substrate 24 is pressed to the main surface of the wafer 1W by pressing the formation surface of the release layer 24a of the support substrate 24 against the adhesive layer 25 on the main surface side of the wafer 1W. Secure to the surface. The peeling layer 24a is a functional layer for facilitating peeling when the support substrate 24 is peeled from the wafer 1W. A so-called BG tape may be used instead of the support substrate.

  Next, as in the first embodiment, after measuring the thickness of the wafer 1W, grinding processing and polishing processing (flat processing) are sequentially performed on the back surface of the wafer 1W based on the measurement result (step 202A2, step 202A2). 202A3). FIG. 42 shows a cross-sectional view after the thinning process of the wafer 1W. The broken line in FIG. 42 shows the substrate 1S before the thinning process.

  Subsequently, the process proceeds to the chip dividing step 202B. The laser irradiation process 202B2 of the chip dividing process 202B is for forming the modified region PR described in the first embodiment. FIG. 43 is a cross-sectional view of main parts of the wafer 1W showing a state in which the laser beam LB1 is irradiated.

  Also in the fourth embodiment, similarly to the first embodiment, the modified region PR is formed on the substrate 1S by irradiating the laser beam LB1 with focus on the inside of the substrate 1S from the back side of the wafer 1W. Form. However, in the fourth embodiment, the laser beam LB1 is irradiated to the planar position on both sides of the metal pattern such as the test pad 1LBt and the boundary or between the chip 1C and the cutting region CR. As described in the first embodiment, the planar shape of the modified region PR may be linearly formed in a planar manner or may be formed in a broken line shape.

  Thereafter, in the wafer mounting step 202B2, the wafer 1W is attached to a jig. 44 is a plan view of the wafer 1W and the jig 7 after the wafer mounting step 202B2 and the WSS peeling step 202B3, and FIG. 45 is a sectional view taken along line X13-X13 in FIG.

  In the wafer mounting step 202B2, the back surface of the wafer 1W is attached to the tape 7a of the jig 7 while the support substrate 24 is attached to the main surface (device forming surface) of the wafer 1W. The wafer 1W is firmly fixed by the adhesive layer 7a2 of the tape 7a. As a result, the wafer 1W is accommodated in the jig 7 with its main surface exposed and exposed.

  Subsequently, in the WSS peeling step 202B3, the laser beam is scanned from end to end of the main surface of the wafer 1W through the transparent support substrate 24 while being focused on the adhesive layer 25 on the main surface of the wafer 1W. Irradiate. Thereby, after peeling off the support substrate 24 from the wafer 1W, the adhesive layer 25 on the main surface of the wafer 1W is removed. The laser light conditions in this step are, for example, an infrared laser with a wavelength of 1064 nm, output: 20 W, irradiation speed: 2000 mm / s, spot diameter: f200 μm. When the adhesive layer 25 is formed of, for example, an ultraviolet curable resin (UV resin), the laser beam uses an ultraviolet laser instead of an infrared laser. Thereby, since the adhesive force of the contact bonding layer 25 can be weakened, the support substrate 24 can be peeled easily.

  Next, in the fourth embodiment, the process proceeds to the TEG processing step 202B4. In the TEG processing step 202B4, the TEG is removed by a dicing saw (blade dicing method) in which the jig 7 containing the wafer 1W is placed on a dicing stage of a dicing apparatus and rotated. FIG. 46 shows a cross-sectional view of the main part of the wafer 1W during this TEG processing step. The dicing saw 26 having a rectangular cross section was used. After the dicing saw 26 is aligned with the cutting region CR, the dicing saw 26 is lowered so as to be in contact with the main surface of the wafer 1W while being rotated. Thus, metal patterns such as the TEG test pad 1LBt and the alignment target Am are removed. FIG. 47 shows a cross-sectional view of the main part of the wafer 1W after the TEG processing step. Here, the metal pattern such as the test pad 1LBt in the cutting region CR is completely removed, and the groove 27 is formed in the cutting region CR on the main surface of the wafer 1W. The depth of the groove 27 is in the middle of the wiring layer 1L, but may reach the substrate 1S. However, the substrate 1S is not completely cut.

  Subsequently, in the dividing step 202B5, as in the first embodiment, the wafer 1W is divided (cut) by the bending method. FIG. 48 shows an enlarged cross-sectional view of the main part of the wafer 1W during the dividing step 202B5. In this case, in general, a crack occurs on one of the two modified regions PR in the cutting region CR, which has a low mechanical strength, and the wafer 1W is cut. In the case of the fourth embodiment, since the metal pattern such as the test pad 1LBt and the alignment target Am is removed, the whisker-like conductor foreign matter does not occur.

  49 is an overall plan view of the chip 1C cut out from the wafer 1W, and FIG. 50 is a cross-sectional view taken along line X14-X14 in FIG. In the case of the fourth embodiment, since the metal pattern such as the test pad 1LBt and the alignment target Am is not left on the outer periphery of the chip 1C, leakage of TEG information can be prevented.

  The subsequent assembly process 202C (202C1 to 202C4, 203A) is the same as the assembly process 102C (102C1 to 102C4, 103A) of the first embodiment, and a description thereof will be omitted.

(Embodiment 5)
In the fourth embodiment, leakage of TEG information can be prevented, but there is a problem that the cutting line described in the third embodiment meanders. In the fifth embodiment, means for avoiding the problem will be described.

  First, similarly to the fourth embodiment, after the back surface processing step 202A of the pre-process 200, the test step 201, and the post-step 202, the process proceeds to the laser irradiation step 202B1 of the chip dividing step 202B. FIG. 51 is a fragmentary cross-sectional view of the wafer 1W during the laser irradiation process in the fifth embodiment. Here, as in the first to fourth embodiments, the laser beam LB1 is irradiated from the back surface of the wafer 1W to the inside of the substrate 1S in a focused manner to form the modified region PR on the substrate 1S. However, in the fifth embodiment, the laser beam LB1 is irradiated to the center in the width direction (short direction) of the cutting region CR. That is, the laser beam LB1 is irradiated to a position that overlaps with a metal pattern such as the test pad 1LBt and the alignment target Am in a plane. As described in the first embodiment, the planar shape of the modified region PR may be linearly formed in a planar manner or may be formed in a broken line shape.

  Subsequently, similarly to the fourth embodiment, after the wafer mounting process 202B2 and the WSS peeling process 202B3, the process proceeds to the TEG processing process 202B4. FIG. 52 is a fragmentary cross-sectional view of the wafer 1W during the TEG processing step 202B4. In this TEG processing step, as in the fourth embodiment, a rotating dicing saw 26 is applied to the cutting area CR on the main surface of the wafer 1W to form a metal pattern such as a test pad 1LBt or an alignment target Am. Remove. However, in the fifth embodiment, a dicing saw 26 having a wedge-shaped (V-shaped cross section) cross-sectional shape at the outer peripheral tip is used.

  53 is a plan view of the main part of the wafer 1W after the TEG processing step, and FIG. 54 is a sectional view taken along line X15-X15 in FIG. Here, the metal pattern such as the test pad 1LBt and the alignment target Am is completely removed, and a groove 27 is formed on the upper surface of the interlayer insulating film 1Li (wiring layer 1L) in the cutting region CR of the main surface of the wafer 1W. Is formed. The depth of the groove 27 is the same as that in the fourth embodiment. However, in the fifth embodiment, the width of the groove 27 gradually becomes narrower as it becomes deeper. That is, the cross-sectional shape of the groove 27 is V-shaped. The deepest portion of the groove 27 is a portion that acts as a dividing starting point of the interlayer insulating film 1Li during the dividing step 202B5. The groove 27 is formed so that the planar position of the portion acting as the division starting point is located in the center in the width direction (short direction) of the cutting region CR, that is, the planar position of the modified region PR (that is, the cutting line CL). ) To match.

  Subsequently, in the dividing step 202B5, as in the first embodiment, the wafer 1W is divided (cut) by the bending method. FIG. 55 shows an enlarged cross-sectional view of the main part of the wafer 1W during the dividing step 202B5. In this case, the wafer 1W is divided (cut) using the modified region PR of the substrate 1S and the groove 27 of the wiring layer 1L as a division starting point.

  In the case of the fifth embodiment, since the metal pattern such as the test pad 1LBt and the alignment target Am is removed, the whisker-like conductor foreign matter does not occur. Further, since the groove 27 is formed in a V-shaped cross section, even if a low dielectric constant film is used as the interlayer insulating film, the wafer 1W (particularly, the interlayer insulating film 1Li on the main surface side of the wafer 1W) is formed in the groove 27. It can be neatly divided (cut) without meandering along. Therefore, the yield and reliability of the semiconductor device can be improved.

  56 is an overall plan view of the chip 1C cut out from the wafer 1W, and FIG. 57 is a sectional view taken along line X16-X16 in FIG. In the case of the fifth embodiment, since the metal pattern such as the test pad 1LBt and the alignment target Am is not left on the outer periphery of the chip 1C, leakage of TEG information can be prevented. In the fifth embodiment, the outer peripheral angle on the main surface side of the chip 1C is inclined. That is, a taper is formed at the outer peripheral angle on the main surface side of the chip 1C. Thereby, it is possible to reduce the lack of the outer peripheral angle of the chip 1C when the chip 1C is conveyed. Therefore, the yield and reliability of the semiconductor device can be improved. Moreover, foreign matter generation can be reduced.

  The subsequent assembly process 202C (202C1 to 202C4, 203A) is the same as the assembly process 102C (102C1 to 102C4, 103A) of the first embodiment, and a description thereof will be omitted.

(Embodiment 6)
In the sixth embodiment, an example of a method for removing TEG with a laser beam to prevent leakage of TEG information will be described.

  First, similarly to the fifth embodiment, after passing through the peeling step 203B3 of the previous step 200 to WSS, the TEG is removed by laser light in the TEG processing step 202B4. FIG. 58 shows a cross-sectional view of the main part of the wafer 1W during the TEG processing step. By irradiating the metal pattern such as the test pad 1LBt and the alignment target Am with the laser beam (second laser) LB3 from the main surface side of the wafer 1W, the metal pattern is melted and removed. As the laser beam LB3, for example, a laser beam having a shorter wavelength than the wavelength of the laser beam LB1 when the modified region PR is formed, such as an ultraviolet beam having a wavelength of 355 nm, is used. The metal pattern is removed by irradiating each metal pattern with the laser beam LB3 a plurality of times. FIG. 59 shows a cross-sectional view of the main part of the wafer 1W after the TEG processing step of the sixth embodiment. Here, the metal pattern such as the test pad 1LBt in the cutting region CR is completely removed. In the case of the sixth embodiment, since the metal pattern can be removed without applying mechanical stress to the wafer 1W by removing the metal pattern in the cutting region CR with the laser beam LB3, damage such as chipping on the outer periphery of the chip 1C. Can be prevented. Thereby, the bending strength of the thin semiconductor chip can be improved as compared with the fourth and fifth embodiments.

  Subsequently, in the dividing step 202B5, as in the first embodiment, the wafer 1W is divided (cut) by the bending method. FIG. 60 shows an enlarged cross-sectional view of the main part of the wafer 1W during the dividing step 202B5. In this case, the wafer 1W is divided (cut) using the modified region PR of the substrate 1S as a division starting point. In the case of the fifth embodiment, since the metal pattern such as the test pad 1LBt and the alignment target Am is removed, the whisker-like conductor foreign matter does not occur.

  The overall plan view of the chip 1C cut out from the wafer 1W in the case of the sixth embodiment is substantially the same as FIG. Also in the case of the sixth embodiment, since no metal pattern such as the test pad 1LBt and the alignment target Am is left on the outer periphery of the chip 1C, leakage of TEG information can be prevented.

  The subsequent assembly process 202C (202C1 to 202C4, 203A) is the same as the assembly process 102C (102C1 to 102C4, 103A) of the first embodiment, and a description thereof will be omitted.

(Embodiment 7)
In the sixth embodiment, leakage of TEG information can be prevented, but there is a problem that the cutting line described in the third embodiment meanders. In the seventh embodiment, means for avoiding the problem will be described.

  First, similarly to the fifth and sixth embodiments, after passing through the peeling step 203B3 of the previous step 200 to WSS, the process proceeds to the TEG processing step 202B4. In this TEG processing step 202B4, the TEG is irradiated with laser light. FIG. 61 shows a cross-sectional view of the main part of the wafer 1W during the TEG processing step 202B4. FIG. 63 shows an enlarged cross-sectional view of the main part of the wafer 1W during the TEG processing step 202B4. Here, similarly to the sixth embodiment, the laser beam LB3 is irradiated from the main surface side of the wafer 1W onto a metal pattern such as the test pad 1LBt and the alignment target Am, thereby testing the cutting region CR. A groove 30 is formed in a part of the metal pattern on the upper surface of the metal pattern such as the pad 1LBt for use and the alignment target Am. The groove 30 is formed by melting by the heat of the laser beam LB3, and the melted portion extends to the interface of the interlayer insulating film 1L1 (wiring layer 1L). As a result, a crack CRK is formed from the groove 30 toward the modified region PR. The planar position of the groove 30 is formed so as to be located at the center in the width direction (short direction) of the cutting region CR, that is, to coincide with the planar position of the modified region PR (that is, the cutting line CL). Yes. Here, in the case of the seventh embodiment, since only a part of the metal pattern in the cutting region CR is removed, damage such as chipping occurs on the outer periphery of the chip 1C just by performing this laser beam processing. There is nothing. Thereby, the bending strength of the thin semiconductor chip can be improved as compared with the fourth and fifth embodiments.

  Subsequently, in the dividing step 202B5, as in the first embodiment, the wafer 1W is divided (cut) by the bending method. FIG. 62 shows an enlarged cross-sectional view of the main part of the wafer 1W during the dividing step 202B5. In this case, the wafer 1W is divided (cut) using the modified region PR of the substrate 1S, the crack CRK, and the groove 30 of the wiring layer 1L as the division starting points.

  In the case of the seventh embodiment, since the cut portion (the groove 30 forming portion) of the metal pattern such as the test pad 1LBt and the alignment target Am is cut, the whisker-like conductor foreign matter is not generated. Further, since the groove 30 reaches the interlayer insulating film 1Li, the wafer 1W (particularly, the interlayer insulating film 1Li on the main surface side of the wafer 1W) is grooved even if a low dielectric constant film is used as the interlayer insulating film. It can be neatly divided (cut) without meandering along 30. Therefore, the yield and reliability of the semiconductor device can be improved.

  Chips 1C cut out from the wafer 1W in the case of the seventh embodiment are substantially the same as those shown in FIGS. Also in the case of the seventh embodiment, a part of the metal pattern such as the test pad 1LBt and the alignment target Am is left on the outer periphery of the chip 1C, but it is cut and melted, and the TEG information. Can not get. Therefore, leakage of TEG information can be prevented. In the seventh embodiment, since the outer peripheral angle on the main surface side of the chip 1C is inclined due to the formation of the groove 30, it is possible to reduce the lack of the outer peripheral angle of the chip 1C during the conveyance of the chip 1C. Therefore, the yield and reliability of the semiconductor device can be improved. Moreover, foreign matter generation can be reduced.

  The subsequent assembly process 202C (202C1 to 202C4, 203A) is the same as the assembly process 102C (102C1 to 102C4, 103A) of the first embodiment, and a description thereof will be omitted.

(Embodiment 8)
In Embodiments 4 and 5, by removing the TEG by a dicing saw (blade dicing method), it is possible to prevent leakage of TEG information and mounting defects caused by TEG whisker-like conductor foreign matter (beard defect). With the demand for further thinning of the semiconductor device, for example, when the thickness of the wafer is as thin as 70 μm or less, the problem of chip cracks is likely to occur as shown in FIG. This is because the dicing saw 26 is used as a TEG removal method, and the distance (interval) from the fractured layer (modified region PR) to the TEG becomes closer (shorter) as the wafer 1W becomes thinner. The bending strength of the wafer 1W (chip 1C) is reduced. The blade dicing method cuts (breaks) the wafer 1W by bringing the dicing saw 26 that rotates at a high speed into contact with the wafer 1W, so that the cutting stress (breaking stress) applied to the wafer 1W is larger than that of the stealth dicing method. That is, as described in the fourth and fifth embodiments, if the TEG is removed using the dicing saw 26 after the laser beam is irradiated on the wafer 1W in advance to form the fracture layer (modified region PR), Since the distance (interval) to the TEG is close and the bending strength of the wafer 1W is lowered, the cutting stress of the dicing saw 26 easily propagates to the fractured layer, and a crack (crack) CRK is generated. End up. Therefore, in the eighth embodiment, means for avoiding the problem will be described.

  First, as shown in FIG. 67, using the dicing saw 26, the test pads 1LBt and the alignment target Am arranged in the cutting region of the main surface of the wafer 1W are removed. Thereby, a groove 27 is formed on the main surface of the wafer 1W.

  Next, as shown in FIG. 68, a BG tape 35 is attached to the main surface of the wafer 1W. The tape base 35a of the BG tape 35 is made of, for example, a flexible plastic material, and an adhesive layer 35b is formed on the main surface thereof. The BG tape 35 is firmly attached to the main surface (chip forming surface) of the wafer 1W by the adhesive layer 35b.

  Subsequently, after the wafer 1W is inverted, as shown in FIG. 69, the back surface of the wafer 1W is formed from the back surface side of the wafer 1W using the grinding and polishing tool (grinding stone) 8 and further back surface grinding process. By performing a polishing process (stress relief) for removing the formed minute unevenness, the wafer 1W is made to have a desired thickness.

  Next, as shown in FIG. 70, the laser beam LB1 is irradiated from the back surface of the wafer 1W, and the modified region (optically damaged portion or crushing) is formed inside the wafer 1W (near the center in the thickness direction) as described above. Layer) PR.

  Next, as shown in FIG. 71, the back surface of the wafer 1W is affixed to the tape 7a of the jig 7, reversed, and then the BG tape 35 on the main surface of the wafer 1W is peeled off (wafer mounting step). Subsequently, as shown in FIG. 72, a plurality of chips 1C are obtained by dividing the wafer 1W by the expanding method.

  As described above, according to the eighth embodiment, each of the test pad 1LBt and the alignment target Am is preliminarily processed by the dicing saw 26 before the back grinding process for thinning the wafer 1W and the process for forming the modified region PR. Therefore, even if the thickness of the wafer 1W is as thin as 70 μm or less, for example, it is possible to suppress the problem of chip cracks.

  Here, when the TEG is removed using the dicing saw 26 after the crushing layer (modified region PR) is formed, when attention is paid only to the problem of chip cracks caused by the cutting stress of the dicing saw 26, the wafer 1W It is also conceivable to form a fractured layer (modified region PR) on the wafer 1W by irradiating the laser beam LB1 from the main surface side of the wafer 1W after removing the TEG from the main surface side of the wafer 1W using the dicing saw 26. It is done.

  However, as shown in FIG. 73, since the surface of the wafer cut by the dicing saw 26 (that is, the bottom surface of the groove 27) is formed with fine irregularities, when the laser beam LB1 is irradiated, irregular reflection occurs, and the wafer It becomes difficult to focus the laser beam LB1 inside 1W.

  Further, after removing the TEG using the dicing saw 26, the wafer 1W is turned over, and a fractured layer (modified region PR) is formed by irradiating a laser beam from the back side of the wafer 1W, and then the thickness of the wafer 1W. Means for carrying out a back grinding process and a polishing process for reducing the thickness of the substrate can also be considered.

  However, if a crush layer (modified region PR) is formed in advance on the wafer 1W before the back grinding process and the polishing process, the crush layer (modified from the back surface of the wafer 1W due to the stress of the grindstone for back grinding). There is a possibility that a crack (crack CRK) may occur toward the quality region PR). From the above, after the TEG is removed by the dicing saw 26 as in the eighth embodiment, the wafer 1W is thinned to a desired thickness by the back grinding process and the polishing process, and the laser beam LB1 is applied from the back side of the wafer 1W. The means for forming a crushed layer (modified region PR) by irradiating is effective for the countermeasure against the problem of chip cracks.

(Embodiment 9)
When the semiconductor wafer is divided by the blade dicing method, a cutting region having a width wider than the width of the dicing saw to be used is necessary. On the other hand, in the case of the stealth dicing method, a crushed layer (modified region PR) is formed inside the semiconductor wafer, and the semiconductor wafer is divided starting from the crushed layer. It can be narrowed.

  However, since the test pad 1LBt and the alignment target Am are arranged in the cutting region CR, at least the width of the cutting region CR needs to be larger than the width of the test pad 1LBt and the alignment target Am. There is. For this reason, it is difficult to improve the number of chips acquired from one wafer. Therefore, in the ninth embodiment, an example of a method for improving the number of chips acquired from one wafer will be described with reference to FIGS. 74, 75, and 76. FIG. 74 is a plan view of the wafer 1W of the ninth embodiment, FIG. 75 is an enlarged plan view of the main part of the main surface of the wafer 1W in FIG. 74, and FIG. 76 is a main part cross-sectional view of the wafer 1W in FIG. It is.

  First, as shown in FIGS. 74 and 75, among the cutting regions CR (CR1, CR2) provided in the X direction and the Y direction (direction intersecting the X direction) on the main surface of the wafer 1W, the X direction The test pad 1LBt and the alignment target Am are arranged only in the cutting region (first cutting region) CR1 provided in the region. That is, the test pad 1LBt and the alignment target Am are not arranged at all in the cutting region (second cutting region) CR2 provided in the Y direction, and the test pad is provided only in the cutting region CR1 provided in the X direction. 1 LBt and alignment target Am are collectively arranged. Thereby, the width of the cutting region CR2 extending in the Y direction can be made narrower than the width of the test pad 1LBt and the alignment target Am. For this reason, the interval between adjacent chips 1C (chip regions) can be further reduced, so that the number of chips 1C acquired from one wafer 1W can be improved. Here, the width of the cutting region CR2 extending in the Y direction is, for example, 5 μm.

  However, when the test pads 1LBt and the alignment target Am are collected in the cutting region CR1 extending in the X direction, as shown in FIG. 75, the testing pads 1LBt and alignment in the cutting region CR1 extending in the X direction. The target Am is arranged over a plurality of rows (two rows in the ninth embodiment). Therefore, when a dicing saw having the same width as the TEG as shown in the fourth, fifth and eighth embodiments is used, in order to completely remove the TEG, dicing is performed on one cutting region CR. You need to run the saw twice. For this reason, the TEG removal process takes time.

  Therefore, in the ninth embodiment, as shown in FIG. 76, it is preferable to use a dicing saw 26 having substantially the same width as the sum of the widths of the two TEGs in the process of removing the TEG pattern. As a result, even if the TEGs are arranged in a plurality of rows in the cutting region CR2, the dicing saw 26 can be removed once and all the TEGs in the cutting region CR2 can be removed. Here, it has been described that the width of the dicing saw 26 is substantially the same as the sum of the widths of the two TEGs. However, at least by running the dicing saw 26 once, all the TEGs in the cutting region CR2 are completely removed. Therefore, it is preferable that the width is equal to or greater than the sum of the widths of the two TEGs and is less than the width of the cutting region CR2.

  In the case of the ninth embodiment, since the moving direction of the dicing saw 26 for removing the TEG pattern is only one direction, the TEG pattern removal processing time can be shortened. Note that the TEG pattern removal processing time can be further shortened by simultaneously operating a plurality of wide dicing saws 26 described in the ninth embodiment in parallel.

(Embodiment 10)
Along with the miniaturization of the semiconductor device, it is required to further reduce the size of the chip. When a stealth dicing method that can cope with the thinning of the wafer is used as a method for dividing the miniaturized chip, in order to divide the wafer into individual chips, an expanding process is performed after irradiating the wafer with laser light. It can be realized by doing.

  However, for example, when forming a chip having a width (length) of 3 mm or less on one side, as shown in FIG. 72 of the eighth embodiment, the entire dicing tape is moved from the center to the outer periphery by one expansion process. When trying to stretch, adjacent chip regions among the plurality of chips 1C (chip regions) are not completely divided, so that a problem of so-called division failure is likely to occur. When the size of one chip is reduced, even if the dicing tape is stretched, the tension is hardly transmitted to each of the plurality of chip regions, and the plurality of chips are connected. Thus, the tenth embodiment describes means for avoiding the problem.

  A plurality of cutting regions CR are provided on one wafer 1W so as to extend in the X direction and the Y direction. In the tenth embodiment, the plurality of cutting regions CR are formed by one expansion process. Are not divided at the same time, but one of the plurality of cutting regions CR is divided by a single expanding process.

  This will be described with reference to a plan view of the wafer 1W in FIG. That is, as shown in FIG. 72, in the first expanding step, first, a cutting region (first cutting region) CR of a is divided. Then, after dividing the cutting region a, the cutting region (second cutting region) CR of b is divided by the second expanding step. Then, the expanding process is repeated until all the cutting regions CR are divided in the order of the cutting regions CR of c, d, e, and f. As a result, even if the width (length) of one side of the chip 1C is reduced, the means of the tenth embodiment is used for each cutting region CR (one line cutting region CR). The tension of the dicing tape can be transmitted reliably. Therefore, it is possible to suppress the problem of division failure. Here, since the wafer 1W is provided with a plurality of cutting regions CR so as to extend in the X direction and the Y direction, a plurality of cutting regions CR provided so as to extend in the X direction. It is preferable to divide a plurality of cutting regions CR provided so as to extend in the Y direction after being divided in order because the dividing mechanism can be simplified.

  Next, the dividing method according to the tenth embodiment will be described more specifically with reference to FIGS. 78 and 79.

  78A is an overall plan view of the wafer 1W showing a specific state of the wafer 1W dividing step described in FIG. 77, and FIG. 78B is a sectional view taken along line X17-X17 in FIG. 79A and 79B are enlarged cross-sectional views of the main part of the wafer 1W during the dividing step.

  As shown in FIG. 78, the wafer 1W attached to the tape 7a of the dicing jig 7 is placed on the stage of the stealth dicing apparatus. On this stage, two planar strip-shaped pulling bars 40 extending from end to end of the wafer 1W along the Y direction in FIG. The width of each pull bar 40 is about the width of the chip 1C of the wafer 1W in the X direction in FIG. 78 (a). Each pulling bar 40 is provided with a vacuum suction hole 41 as shown in FIG. Thus, the pull bar 40 can be firmly attached to the wafer 1W via the tape 7a of the dicing jig 7, and the wafer 1W can be fixed.

  First, in order to divide only one cutting region CR (one line cutting region CR), as shown in FIGS. 78 and 79, one line cutting region CR of the wafer 1W has two pull bars 40. After positioning the wafer 1W so as to planarly overlap between adjacent portions (cutting grooves), two tension bars 40 are attached to the wafer 1W by vacuum suction. That is, the two pull bars 40 are arranged and fixed on both sides of the divided region (cut region CR for one line) as a boundary.

  Subsequently, in a state where the wafer 1W is vacuum-sucked by the two pull bars 40, the two pull bars 40 are indicated by arrows PA and PB (directions along the main surface of the wafer 1W) in FIGS. 78 and 79, respectively. Move away from each other. That is, the two pull bars 40 are moved in the direction of pulling outward from between the adjacent bars. As a result, as shown in FIG. 79 (b), the wafer 1W fixed to the pull bar 40 is divided starting from the cutting region (the modified region PR).

  When the division of one cutting region CR (cutting region CR for one line) is completed, the wafer 1W is moved so that the cutting region CR to be divided next overlaps adjacently between the two pull bars 40 in a plane. . Thereafter, the wafer 1W is divided in the same manner as described above. By repeating the above operation until all of the cutting areas CR of a plurality of lines are divided, a plurality of chips 1C can be obtained without causing a division failure.

  Here, in the tenth embodiment, the case where two pull bars 40 are formed as one set has been described. However, the present invention is not limited to this, and the number corresponding to the cutting regions CR of a plurality of lines of the wafer 1W. Only the pull bar 40 may be arranged. This eliminates the need to shift the wafer 1W each time one expansion process is completed. 80 (a) to (c) show an example thereof. CL1 indicates a first division location, CL2 indicates a second division location, and CL3 indicates a third division location. The wafer 1W is divided in the same manner as described above by moving the pulling bars 40 on both sides of the divided portions CL1, CL2, and CL3 in directions away from each other (directions of arrows PA and PB).

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment, the planar shape of the test pad 1LBt is square. However, the planar shape of the test pad 1LBt is not limited to this and can be variously changed. For example, the planar shape of the test pad 1LBt is rectangular ( The length of the cutting region CR in the extending direction (longitudinal direction) may be longer than the length of the cutting region CR in the width direction. Thereby, a large area of the pad 1LBt can be secured without increasing the width of the cutting region CR so much. That is, it is possible to ensure the ease of applying the probe needle to the test pad 1LBt while suppressing an increase in the area of the chip 1C.

  In the third embodiment, the laser beam LB2 is irradiated from the back surface of the wafer 1W to form the hole 21 in the metal pattern of the cutting region CR on the main surface of the wafer 1W. When performing the wafer mounting process as described in, the laser beam LB2 can be irradiated from the main surface of the wafer 1W. In this case, a laser beam LB2 irradiation step may be performed instead of the TEG processing step 202B4 of FIG. That is, the test pad 1LBt, the alignment target Am, and the metal pattern 20 are irradiated from the main surface side of the wafer 1W to the test pad 1LBt, the alignment target Am, and the metal pattern 20 from the main surface side of the wafer 1W. Holes 21 are formed in the target Am and the metal pattern 20. In this case, grooves may be formed in the test pad 1 LBt, the alignment target Am, and the metal pattern 20 in place of the holes 21. The planar shape of the groove may be a straight line or a broken line. The other steps are the same as those described in the first to seventh embodiments.

  In the above description, the case where the invention made mainly by the present inventor is applied to the method of manufacturing a semiconductor device which is a field of use as the background has been described. However, the present invention is not limited to this and can be applied in various ways. It can also be applied to a micromachine manufacturing method.

  The present invention can be applied to a product manufacturing industry having a process of dividing a wafer by stealth dicing.

Claims (20)

A substrate having a main surface, a back surface opposite to the main surface, and a side surface between the main surface and the back surface;
An interlayer insulating film formed on the main surface;
A pad formed on the interlayer insulating film;
A protective film formed on the interlayer insulating film to expose the pad;
A modified region formed on the substrate;
Including
The interlayer insulating film has a wiring layer and a low dielectric constant film,
The substrate is made of silicon;
The dielectric constant of the low dielectric constant film is lower than the dielectric constant of the substrate,
The modified region is a semiconductor chip formed on the side of the substrate with respect to the pad. In claim 1,
The modified region is a semiconductor chip in contact with the side surface of the substrate. In claim 1,
A semiconductor chip in which an integrated circuit is formed on the main surface of the substrate. In claim 1,
The low dielectric constant film is a semiconductor chip that is more fragile than the substrate. In claim 1 or claim 4,
The low dielectric constant film is a semiconductor chip made of organic polymer or organic silica glass. A substrate;
A semiconductor chip mounted on the substrate;
Including
The semiconductor chip is
A substrate having a main surface, a back surface opposite to the main surface, and a side surface between the main surface and the back surface;
An interlayer insulating film formed on the main surface;
A pad formed on the interlayer insulating film;
A protective film formed on the interlayer insulating film to expose the pad;
A modified region formed on the substrate;
Have
The interlayer insulating film is
A wiring layer;
A low dielectric constant film;
Have
The substrate is made of silicon;
The dielectric constant of the low dielectric constant film is lower than the dielectric constant of the substrate,
The modified region is a semiconductor device formed on the side surface of the substrate with respect to the pad. In claim 6,
The modified region is a semiconductor device in contact with the side surface of the substrate. In claim 6,
A semiconductor device in which an integrated circuit is formed on the main surface of the substrate. In claim 6,
The low dielectric constant film is a semiconductor device that is more fragile than the substrate. In claim 6 or claim 9,
The low dielectric constant film is a semiconductor device made of organic polymer or organic silica glass. A substrate having a main surface, a back surface opposite to the main surface, and a side surface between the main surface and the back surface;
An interlayer insulating film formed on the main surface;
A plurality of pads formed along the first side of the main surface and on the interlayer insulating film;
A protective film formed on the interlayer insulating film so as to expose the plurality of pads;
A modified region formed along the first side of the main surface;
Including
The interlayer insulating film has a wiring layer and a low dielectric constant film,
The substrate is made of silicon;
The dielectric constant of the low dielectric constant film is lower than the dielectric constant of the substrate,
The modified region is a semiconductor chip formed on the side surface of the substrate with respect to the plurality of pads. In claim 11,
The modified region is a semiconductor chip in contact with the side surface of the substrate. In claim 11,
A semiconductor chip in which an integrated circuit is formed on the main surface of the substrate. In claim 11,
The low dielectric constant film is a semiconductor chip that is more fragile than the substrate. In claim 11 or claim 14,
The low dielectric constant film is a semiconductor chip made of organic polymer or organic silica glass. A substrate;
A semiconductor chip mounted on the substrate;
Including
The semiconductor chip is
A substrate having a main surface, a back surface opposite to the main surface, and a side surface between the main surface and the back surface;
An interlayer insulating film formed on the main surface;
A plurality of pads formed along the first side of the main surface and on the interlayer insulating film;
A protective film formed on the interlayer insulating film so as to expose the plurality of pads;
A modified region formed along the first side of the main surface;
Have
The interlayer insulating film is
A wiring layer;
A low dielectric constant film;
Have
The substrate is made of silicon;
The dielectric constant of the low dielectric constant film is lower than the dielectric constant of the substrate,
The modified region is a semiconductor device formed on the side surface side of the substrate with respect to the plurality of pads. In claim 16,
The modified region is a semiconductor device in contact with the side surface of the substrate. In claim 16,
A semiconductor device in which an integrated circuit is formed on the main surface of the substrate. In claim 16,
The low dielectric constant film is a semiconductor device that is more fragile than the substrate. In claim 16 or claim 19,
The low dielectric constant film is a semiconductor device made of organic polymer or organic silica glass.

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