JPS58137209A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58137209A JPS58137209A JP2021282A JP2021282A JPS58137209A JP S58137209 A JPS58137209 A JP S58137209A JP 2021282 A JP2021282 A JP 2021282A JP 2021282 A JP2021282 A JP 2021282A JP S58137209 A JPS58137209 A JP S58137209A
- Authority
- JP
- Japan
- Prior art keywords
- wafer
- chips
- fabricated
- semiconductor
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
Abstract
Description
【発明の詳細な説明】
この発明は半導体装置の製造方法に係り、特に複数個の
半導体チップ（以下「テップ」と略称する）を一枚の半
導体ウェーハ（以下「ウェーハ」と略称する）に作り込
む方法に関するものである。[Detailed Description of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly relates to a method for manufacturing a semiconductor device, and in particular, a method for manufacturing a semiconductor device, in which a plurality of semiconductor chips (hereinafter abbreviated as "Tep") are formed into a single semiconductor wafer (hereinafter abbreviated as "wafer"). This is related to the method of embedding.
第１図は従来の方法によって複数個のチップを一枚のウ
ェーハに作り込んだ状態の一例を示す平面図である。FIG. 1 is a plan view showing an example of a state in which a plurality of chips are fabricated on one wafer by a conventional method.
図において、（１）は円板状のウェーハ、（２）はウェ
ーハ（１）にＸ方向およびＹ方向にそれぞれ複数個互い
に隣接して整列するように作り込まれた大容量の形状の
大きいチップ、（３）は各チップ（２）を取り囲むよう
にＸ方向およびＹ方向にレーザー光、ダイヤモンドカッ
タなどを用いて形成されウェーハ（１）を個々のチップ
（２）に分割するためのスクライプラインである。In the figure, (1) is a disk-shaped wafer, and (2) is a large-capacity, large-sized chip fabricated on wafer (1) so that a plurality of chips are arranged adjacent to each other in the X direction and the Y direction. , (3) are scribe lines formed using a laser beam, a diamond cutter, etc. in the X and Y directions to surround each chip (2), and are used to divide the wafer (1) into individual chips (2). be.
ところで、この従来例の方法では、ウェーハ（１１のチ
ップ（２）を作り込むことができない周縁部を、ウェー
ハ０１が個々のチップ（２）に分割された後に、捨てて
しまうどとになるので、チップ（２）の形状が大きくな
るに連れてウェーハ＋１１の利用率が低下するという欠
点があった。By the way, in this conventional method, the peripheral portion of the wafer (11) where chips (2) cannot be fabricated is discarded after the wafer 01 is divided into individual chips (2). However, as the shape of the chip (2) becomes larger, the utilization rate of wafer +11 decreases.
この発明は、上述の欠点に鑑みてなされたもので、ウェ
ーハの第１のチップが作り込まれた残余の周縁部にこの
第１のチップの形状より小さい形状の第２のチップを作
り込むことＫよって、ウェーハの利用率を向上させ得る
半導体装置の製造方法を提供することを目的とする０
第２図はこの発明の一実施例の方法によって複数個のチ
ップを一枚のウェーハに作り込んだ状態を示す平面図で
ある。This invention has been made in view of the above-mentioned drawbacks, and involves manufacturing a second chip having a smaller shape than the first chip in the remaining peripheral edge of the wafer where the first chip has been created. Therefore, it is an object of the present invention to provide a method for manufacturing a semiconductor device that can improve the utilization rate of a wafer. FIG. FIG.
図において、第１図に示した従来例の符号と同一符号は
同一部分を示し、その説明は省略する。In the figure, the same reference numerals as those in the conventional example shown in FIG. 1 indicate the same parts, and the explanation thereof will be omitted.
ｔ４Ｈｓｔウェーハ（１）のテップ（２）が作り込まれ
た残余の周縁部に作り込まれチップ（２）の形状より小
さい形状を有するチップである。This chip is manufactured in the remaining peripheral portion of the t4Hst wafer (1) where the tip (2) is manufactured and has a smaller shape than the chip (2).
この実施例の方法では、ウェーハ（１）が個々のチップ
（２）および（４）Ｋ分割された後に、ウェーハ（１）
の捨てられる部分を極めて少なくすることが可能となり
、ウェーハ（１）の利用率を第１図に示した従来例の場
合における利用率よシ向上させることができる。In the method of this example, after the wafer (1) is divided into individual chips (2) and (4)K, the wafer (1)
It becomes possible to extremely reduce the portion of the wafer (1) that is discarded, and the utilization rate of the wafer (1) can be improved compared to that of the conventional example shown in FIG.
以上、説明したように、この発明の半導体装置の製造方
法では、ウェーハの第１のチップが作り込まれた残余の
周縁部にこの第１のチップの形状より小さい形状の第２
のチップを作り込むので、上記ウェーハが個々の上記第
１および第２のチップに分割された後に、上記ウェーハ
の捨てられる部分管極めて少々くすることが可能となシ
、上記As described above, in the method for manufacturing a semiconductor device of the present invention, a second chip having a shape smaller than that of the first chip is formed on the remaining peripheral edge of the wafer where the first chip is formed.
chips, so that after the wafer is divided into individual first and second chips, it is possible to reduce the number of parts of the wafer that are discarded to a very small extent.
第１図は従来の方法によって複数個のチップを一枚のウ
ェーハに作り込んだ状態の一例を示す平面図、第２図は
この発明の一実施例の方法罠よって複数個のチップを一
枚のウェーハに作り込んだ状態を示す平面図である。
図において、１１１Ｆ１半導体ウェーハ、（２）および
（４）はそれぞれ第１および第２の半導体チップである
◎なお、図中同一符号はそれぞれ同一もしくは相当部分
を示す。FIG. 1 is a plan view showing an example of a state in which a plurality of chips are fabricated on one wafer by a conventional method, and FIG. FIG. In the figure, the 111F1 semiconductor wafer, (2) and (4) are the first and second semiconductor chips, respectively. In the figure, the same reference numerals indicate the same or corresponding parts, respectively.
Claims (1)
体ウェーハの上記第１の半導体チップが作り込まれた残
余の周縁部に上記第１の半導体チップの形状より小さい
形状を有する第２の半導体チップを作り込むことを特徴
とする半導体装置の製造方法０il+ A second semiconductor chip having a shape smaller than the shape of the first semiconductor chip is placed on the remaining periphery of the semiconductor wafer on which the first semiconductor chips are formed. Method 0 of manufacturing a semiconductor device characterized by manufacturing
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021282A JPS58137209A (en) | 1982-02-09 | 1982-02-09 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2021282A JPS58137209A (en) | 1982-02-09 | 1982-02-09 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS58137209A true JPS58137209A (en) | 1983-08-15 |
Family
ID=12020854
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2021282A Pending JPS58137209A (en) | 1982-02-09 | 1982-02-09 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58137209A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188952A (en) * | 1983-04-11 | 1984-10-26 | Shinko Electric Ind Co Ltd | Manufacture of lead frame |
| JPS63108706A (en) * | 1986-10-27 | 1988-05-13 | Toshiba Corp | Manufacture of semiconductor device |
-
1982
- 1982-02-09 JP JP2021282A patent/JPS58137209A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59188952A (en) * | 1983-04-11 | 1984-10-26 | Shinko Electric Ind Co Ltd | Manufacture of lead frame |
| JPH0135503B2 (en) * | 1983-04-11 | 1989-07-25 | Shinko Elec Ind | |
| JPS63108706A (en) * | 1986-10-27 | 1988-05-13 | Toshiba Corp | Manufacture of semiconductor device |
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