JPS59197151A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To control an IC device easily by previously preparing a wafer, to which a master process is completed beforehand, and using one or plural fundamental chips in response to the scale of an IC to be prepared when single or plural kinds of fundamental unit elements are formed on the wafer. CONSTITUTION:Fundamental chips 5 to which active elements 2 and circuit elements 3 for inputs/outputs are formed are shaped previously through a chip isolation region 4. On the other hand, regions in which one chips 5 are mounted are formed surrounded by scribing lines 6 and a plurality of pads 1 are shaped previously to the peripheral sections of the regions in a master wafer loading these chips 5. Accordingly, the number of the fundamental chips is selected in response to the scale of an IC circuit to be prepared, and the chips are fixed onto loading regions, and mutually connected desirably by using the pads 1. That is, wirings in the fundamental chips and wirings in the isolation region are formed separately, and the burden of a computer system for the wirings is lightened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to a method for configuring an integrated circuit device using a master slice method.

[Prior art and its problems]

In the recent development of Izumi tJz circuits, one of the requirements is to shorten the time from design to commercialization, and one method is the mask-slice method.QThis method is
The process is divided into a master process in which active and passive elements are created in advance on silicon substrate, and a wiring process in which metal wiring is applied to those active and passive elements to realize an integrated circuit device. This method uses a general-purpose master wafer manufactured in the master process to create integrated circuits for individual purposes in the wiring process.

An integrated circuit device that uses this master slice method is a gate array, which is a structure in which basic unit elements are arranged in an array on a chip, and these can be designed by wiring using a computer system and acquisition. Combined, the entire circuit is realized.

Until now, when designing and manufacturing a gate array, as shown in Fig. 1, a master unit is used, in which a basic element row 3 in which basic unit elements are arranged in an array, and an input/output circuit element 2 are formed. Metal wiring is placed on the chip that has completed the process to configure the circuit. ◇With this type of master chip configuration, it is necessary to prepare various master wafers depending on the scale of the integrated circuit device being designed. , and when realizing a large-scale integrated circuit, using a master chip with many basic unit elements α will increase the burden on the computer system.

[Purpose of the invention]

The present invention is an improvement on the conventional technology in order to solve the above-mentioned disadvantages, and the scale of the integrated circuit to be manufactured can be adjusted by using one type of wafer that has completed the master process prepared in advance. Depending on the situation, an integrated circuit is realized by having one or more basic chips all around.

Another objective is to reduce the burden on a computer system by using a hierarchical wiring method when constructing a large-scale integrated circuit using a plurality of basic chips.

[Summary of the invention - Ushio]

The present invention, as shown in FIG. 2, consists of a VC: 1, a basic unit element array, 3, an element for a circuit circuit, 2, and other active elements, and a basic chip that includes only a wiring area within the chip; This is a method of configuring a master wafer consisting of two basic chip isolation regions, which serve as a 2-butt self-chamber area and a scribe line or a wiring area between basic chips.

Therefore, when designing a wiring process, when realizing a small-scale integrated circuit with a sufficient number of elements in one basic chip,
Place pads and scribe lines in the chip isolation area. In addition, when configuring a large-scale integrated circuit that spans multiple basic chips, a part of the chip separation area can be used as a wiring area to connect the circuits realized on each basic chip. Pads and scribe lines are placed only in the isolated areas.

〔Effect of the invention〕

By using the master wafer construction method of the present invention, several types of master wafers, which were conventionally prepared in advance due to differences in the number of basic elements, can be reduced to only one type, making management easier.

If a conventional master with a large number of basic elements is used to realize a large-scale integrated circuit, the burden on the computer system for wiring increases as the circuit scale increases.

However, in the present invention, by separating the wiring within the basic chip and the wiring within the isolation area and using a 19-machine system, it is possible to lighten the burden. When constructing an integrated circuit using a master wafer consisting of various basic chips and their isolation regions,
Depending on the scale of the integrated circuit device being designed, it is possible to use one or more basic chips to create an entire circuit system.

First, in the case of a system that is relatively small-scale and can be realized within one basic chip, a circuit with basic unit elements connected (-8 design) is constructed within the basic chip in the wiring process using a computer, and at the same time A pad 1 and a scribe line 6 are placed in the isolation region, and one basic chip is used.
An integrated circuit can be created and is shown in FIG.

Next, a large-scale circuit system is constructed using the method of the present invention.
A complete example of the implementation is shown in FIG. In a large-scale integrated circuit, L1' cannot be established within one basic chip. In the case of Figure 4, four basic chips are used, and the enclosed isolation area is used as the wiring area 7 between all the basic chips, and only the outer isolation area is used as the pad 1 and scribe line 6. use. By handling the layouts within the basic chip and between the basic chips separately during the wiring process using a computer, a large-scale integrated circuit device can be constructed with a small burden on the computer.

In this example, four basic chips are used, but it goes without saying that any fixed number of chips can be used.

[Brief explanation of the drawing]

Fig. 1 is a plan view of the structure of a master chip of a conventional gate array, Fig. 2 is a plan view of the structure of a master chip according to the present invention, and Fig. 3 is a plan view of the structure of a master chip of a conventional gate array. FIG. 4 is a plan view of a completed circuit system made up of basic chips, and FIG. 4 is a plan view of a large-scale integrated circuit system realized using a plurality of basic chips. In the figure, 1... Pad, 2... Input/output circuit element, 3...
Basic unit element, 4... Basic chip isolation region, 5...
Basic chip, 6. Scribe line, 7... Wiring area between basic chips, 8... Metal wiring between basic chips. Agent: Patent attorney Kensuke Norichika and 1 other person @2 Figure 8 Figure 4

Claims (1)

[Claims] Singular is also 1. 〈〉 consists of a basic chip area of the same shape consisting only of multiple types of basic unit elements, and a chip separation area that is determined by the wiring process to be either a pad and scribe line or a wiring area between basic chips.
A semiconductor integrated circuit device characterized in that it consists of two areas.