JPS5928359A - Manufacture of integrated circuit device - Google Patents
Manufacture of integrated circuit deviceInfo
- Publication number
- JPS5928359A JPS5928359A JP57139013A JP13901382A JPS5928359A JP S5928359 A JPS5928359 A JP S5928359A JP 57139013 A JP57139013 A JP 57139013A JP 13901382 A JP13901382 A JP 13901382A JP S5928359 A JPS5928359 A JP S5928359A
- Authority
- JP
- Japan
- Prior art keywords
- chips
- chip
- integrated circuit
- circuit device
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 5
- 238000000034 method Methods 0.000 claims abstract description 16
- 238000012545 processing Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 2
- 238000011161 development Methods 0.000 description 4
- 241000288673 Chiroptera Species 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005192 partition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
発明の属する技術分野の説明
本発明はマスタースライス方式の集積回路装置の製造方
法に関するものである。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for manufacturing a master slice type integrated circuit device.
従来技術の説明
従来マスタースライス方式の大規模集積回路装置は１ウ
エーハー上に同一回路の複数のセルを持った共通の下地
に品種各に異なる配線全行なって各々の種類の集積回路
装置を作っており１ウエーハー内には同一の配線処Ｒを
行ない同一のチップが作られていた。すなわち第１図に
示すように、ケース１−１内に同一のチップ３−１を設
け、配＠４−１でパッド３−１と接続している。Description of the Prior Art Conventionally, large-scale integrated circuit devices using the master slice method are made by performing different wiring for each product type on a common substrate with multiple cells of the same circuit on one wafer to create each type of integrated circuit device. In one wafer, the same wiring process R was performed and the same chips were manufactured. That is, as shown in FIG. 1, the same chip 3-1 is provided in the case 1-1 and connected to the pad 3-1 through the wiring @4-1.
しかし最近大規模集積回路化するにつれシステムの主要
機能はほとんど集積回路化されつつあシ、その中でも少
数多品種のものはマスタースライス方式で集積回路装置
を作る傾向にある。マスタースライス方式の利点は開発
期間が短かく安い開発費で大規模集積回路装置を作れる
ことにあります。However, with the recent trend toward large-scale integrated circuits, most of the main functions of systems have been integrated into integrated circuits, and among these, there is a tendency to manufacture integrated circuit devices using the master slice method for a small number of high-mix products. The advantage of the master slice method is that it can produce large-scale integrated circuit devices with a short development period and low development costs.
しかし回路規模が大きくなると１チツプの中に収ま力き
れず、回路を分割するか専用に開発する方法がとられて
いた。回路を分割すれば複数で１機能分のものとなシ専
用に開発すれば開発期間が長くなり、いずれに於ても開
発費のみならず製品単価も割高とならざるをえなかった
。However, as the scale of the circuit increased, it could not be accommodated on a single chip, so the approach was to divide the circuit or develop a dedicated circuit. If the circuit is divided into multiple circuits, one function will be divided into multiple circuits.If the circuit is developed exclusively for one function, the development period will be longer, and in both cases, not only the development cost but also the unit price of the product must be relatively high.
発明の目的・構成の説明
本発明の目的は従来技術の欠点を除去することで、その
特徴は上記回路規模が大きく１チツプに入らないものを
別チップに分割して構成した機能を、同一マスタースラ
イスの下地のウェーハー上にとなシ合わて配置し、各々
のチップ内の配線と各チップ間の配線を行なうことによ
シ、実質的に１チツプ化とした大規模集積回路装置にあ
る。Description of Purpose and Structure of the Invention The purpose of the present invention is to eliminate the drawbacks of the prior art, and its feature is that the above-mentioned circuits that are too large to fit on one chip can be divided into separate chips, and the functions can be integrated into the same master. By arranging the circuits side by side on a wafer underlying the slice and performing wiring within each chip and wiring between each chip, the large-scale integrated circuit device is substantially integrated into one chip.
発明の効果
本発明のマスタースライス方式の大規模集積回路の効果
は、早く安く開発できることにある。従ってンステムの
規模が大きく集積回路化する回路構成が大きくて１チツ
プ内に入らないものを実質１チツプ化して１個のケース
に収めて製品化するため従来同一ウェーハー上には同一
回路の配線処理よシなされなかったものをとなり合うチ
ップ同しで異なる配線処理を行ない、各々のチップ同じ
の接続も同一配線処理で行なうことによシ、実質的に１
機能１チップ化の大規模集積回路装置を構成することが
できる。Effects of the Invention The advantage of the master slice type large-scale integrated circuit of the present invention is that it can be developed quickly and inexpensively. Therefore, if the scale of the system is large and the circuit structure to be integrated into an integrated circuit is too large to fit on one chip, it is essentially integrated into one chip and housed in one case for commercialization. By using the same wiring process to connect the same chips to each other, and using the same wiring process to connect the same chips to each other, it is possible to effectively
A large-scale integrated circuit device with a single functional chip can be constructed.
この発明の詳細な説明 次に本発明の実施例を図面を参照して説明する。Detailed description of this invention Next, embodiments of the present invention will be described with reference to the drawings.
第１図は従来方法で製造された大規模集積回路装置を示
しチップと配線の関係がわかるように蓋を外した状態を
表わしている。FIG. 1 shows a large-scale integrated circuit device manufactured by a conventional method, with the lid removed so that the relationship between chips and wiring can be seen.
第２図は本発明によシ組立てられたものの例を示し、第
３図は本発明によるウェーハー上のとなシ合う同一機能
を２分割して配置配線をした２チツプ分の拡大図を示す
。第１図の方法では集積度を大きくして１機能１チップ
化するか分割して複数構成にするしかないが、第２図の
ように１個のケースに２チツプ収容し１機能分を２チツ
プに分割して配置すれば、実質１チツプ化と同等の機能
が得られる。第２図に示す２−２と２−３のチップを電
気的に接続する配線５を作る方法として第３図に示すよ
うに、同一マスタースライスの下地のウェーハー上のと
なシ同しに２−２と２−３に対シて２−４と２−５のチ
ップを配置し、チップの外との配線用パラ）３−１〜３
−５のうち、２−４と２−５のとなシ合った側の３−４
と３−５のバット同しで配線する５−２の接続方法や、
それぞれのセルから直接接続する５−３の接続方法によ
り、２−４と２−５同じを接続できるように配線用マス
クを作ることによシ、両チップ同じを直接電気的に接続
できる。FIG. 2 shows an example of a chip assembled according to the present invention, and FIG. 3 is an enlarged view of two chips in which identical functions on a wafer are divided into two and placed and routed according to the present invention. . In the method shown in Figure 1, the only option is to increase the degree of integration and make one chip for each function, or to divide it into multiple configurations, but as shown in Figure 2, two chips for one function can be accommodated in one case. By dividing it into chips and arranging it, you can essentially obtain the same functionality as a single chip. As shown in FIG. 3, a method for making the wiring 5 that electrically connects the chips 2-2 and 2-3 shown in FIG. Place the chips 2-4 and 2-5 against the chips 2 and 2-3, and connect the chips to the outside of the chip using the parallax 3-1 to 3.
-5, 3-4 on the side of 2-4 and 2-5
5-2 connection method of wiring with the same bat as 3-5,
By the connection method 5-3, which connects directly from each cell, by making a wiring mask so that the same chips 2-4 and 2-5 can be connected, both chips can be directly electrically connected.
配線されたチップを１個ずつに切離すときは第３図に示
すスクライプｌｆＭ６−１〜６−４で切シ、チップ２−
４と２−５間の６−５は切らないで２゛−４と２−５は
１体のチップとして扱うことによシ、実質的に第２図に
示すように１個のケース内に１機能の集積回路を構成す
ることができる。When cutting the wired chips one by one, use the scribers lfM6-1 to 6-4 shown in Figure 3 to cut the chips 2-
By not cutting 6-5 between 4 and 2-5 and treating 2-4 and 2-5 as one chip, they are essentially placed in one case as shown in Figure 2. A single-function integrated circuit can be constructed.
本発明は以上説明したように同一ウェーハーに１機能を
分割して別々のチップにそれぞれの配線を施したとなシ
合うチップｆ、１体として処理することによシｌチップ
に入らない大規模回路の実質１チツプ化構成のマスター
スライズ方式大規模集積回路装置とする効果がある。As explained above, the present invention is capable of processing large-scale chips that do not fit into a single chip by dividing one function on the same wafer and wiring each chip on separate chips. This has the effect of creating a master slide type large-scale integrated circuit device in which the circuit is substantially integrated into one chip.
第１図は１ケース１チツプ収容の従来方式の集積回路装
置を示す図、第２図は１機能２チップに分割されたもの
を１ケース内に収容した例の集積回路装置を示す図、第
３図は本発明による同一ウェーハー内のとなりあうチッ
プに１機能を分割して配置した場合の２チツプの拡大図
を示す。
尚、図において、ｌ−１，１−２・・・・・集積回路装
置のケース、２−１〜２−５・・・・・・集積回路のチ
ップ、３−１〜３−５・・・・・・チップの外との接続
のためのバット、４−１〜４−３・・・・・・チップと
ケース端子間を電気的に接続する配線、５−１〜５−３
となり合うチップ回し全電気的に接続するための配線パ
ターン、６−１〜６−４・・・・・・ウェーハーをチッ
プ各に切離すための切断線、６−５・・・・・・１対と
なる両チップ間の仕切線を示す。Fig. 1 shows a conventional integrated circuit device in which one chip is housed in one case, and Fig. 2 shows an example integrated circuit device in which two chips per function are housed in one case. FIG. 3 shows an enlarged view of two chips in which one function is divided and placed on adjacent chips in the same wafer according to the present invention. In the figure, l-1, 1-2...case of integrated circuit device, 2-1 to 2-5... chip of integrated circuit, 3-1 to 3-5... ... Bats for connecting the chip to the outside, 4-1 to 4-3 ... Wiring for electrically connecting the chip and case terminals, 5-1 to 5-3
Turning adjacent chips Wiring pattern for electrical connection, 6-1 to 6-4... Cutting line for separating the wafer into chips, 6-5...1 The partition line between the two chips forming a pair is shown.
Claims (2)
マスタースライス方式の大規模集積回路装置において、
同一ウェーハー上に異なる配線のチップを構成すること
を特徴とする集積回路装置の製造方法。(1) In a large-scale integrated circuit device using the master slice method, which is manufactured by performing a wiring processing process on a pre-prepared base,
A method for manufacturing an integrated circuit device, characterized by configuring chips with different wiring on the same wafer.
チップとして配線されたチップ同しをとなり合わせて配
置し、チップ同じ間の接続をウェーハー上の配線処置で
接続することを特徴とする特許請求の範囲第（１）項記
載の集積回路装置の製造方法。(2) The arrangement of the chips is characterized in that chips having the same function divided and wired as separate chips are arranged next to each other, and connections between the chips are connected by wiring on the wafer. A method for manufacturing an integrated circuit device according to claim (1).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57139013A JPS5928359A (en) | 1982-08-10 | 1982-08-10 | Manufacture of integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57139013A JPS5928359A (en) | 1982-08-10 | 1982-08-10 | Manufacture of integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5928359A true JPS5928359A (en) | 1984-02-15 |
Family
ID=15235435
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57139013A Pending JPS5928359A (en) | 1982-08-10 | 1982-08-10 | Manufacture of integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5928359A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151939A (en) * | 1984-08-22 | 1986-03-14 | Nec Corp | Semiconductor wafer |
| JPS6163842U (en) * | 1984-09-29 | 1986-04-30 | ||
| JPS63258042A (en) * | 1987-04-15 | 1988-10-25 | Nec Kyushu Ltd | Semiconductor device |
| US4930000A (en) * | 1985-05-31 | 1990-05-29 | Siemens Aktiengesellschaft | Terminal assembly for an integrated semiconductor circuit |
-
1982
- 1982-08-10 JP JP57139013A patent/JPS5928359A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151939A (en) * | 1984-08-22 | 1986-03-14 | Nec Corp | Semiconductor wafer |
| JPS6163842U (en) * | 1984-09-29 | 1986-04-30 | ||
| US4930000A (en) * | 1985-05-31 | 1990-05-29 | Siemens Aktiengesellschaft | Terminal assembly for an integrated semiconductor circuit |
| JPS63258042A (en) * | 1987-04-15 | 1988-10-25 | Nec Kyushu Ltd | Semiconductor device |
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