UST101804I4 - Integrated circuit layout utilizing separated active circuit and wiring regions - Google Patents

Integrated circuit layout utilizing separated active circuit and wiring regions Download PDF

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Publication number
UST101804I4
UST101804I4 US06146909H US101804DH UST101804I4 US T101804 I4 UST101804 I4 US T101804I4 US 06146909 H US06146909 H US 06146909H US 101804D H US101804D H US 101804DH US T101804 I4 UST101804 I4 US T101804I4
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US
United States
Prior art keywords
conductors
logic cells
elongated
wiring regions
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
US06146909H
Inventor
John Balyoz
Algirdas J. Grwodis
Filing date
Publication date
Application filed filed Critical
Application granted granted Critical
Publication of UST101804I4 publication Critical patent/UST101804I4/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Geometry (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.
US06146909H 1980-05-05 Integrated circuit layout utilizing separated active circuit and wiring regions Pending UST101804I4 (en)

Publications (1)

Publication Number Publication Date
UST101804I4 true UST101804I4 (en) 1982-05-04

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ID=2171280

Family Applications (1)

Application Number Title Priority Date Filing Date
US06146909H Pending UST101804I4 (en) 1980-05-05 Integrated circuit layout utilizing separated active circuit and wiring regions

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US (1) UST101804I4 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517040A (en) * 1987-04-30 1996-05-14 International Business Machines Corporation Personalizable semiconductor chips for analog and analog/digital circuits
US5949098A (en) * 1995-06-15 1999-09-07 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5517040A (en) * 1987-04-30 1996-05-14 International Business Machines Corporation Personalizable semiconductor chips for analog and analog/digital circuits
US5949098A (en) * 1995-06-15 1999-09-07 Oki Electric Industry Co., Ltd. Semiconductor integrated circuit having an improved arrangement of power supply lines to reduce noise occurring therein

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