JPS564265A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS564265A
JPS564265A JP8004779A JP8004779A JPS564265A JP S564265 A JPS564265 A JP S564265A JP 8004779 A JP8004779 A JP 8004779A JP 8004779 A JP8004779 A JP 8004779A JP S564265 A JPS564265 A JP S564265A
Authority
JP
Japan
Prior art keywords
wires
cells
displaced
chip
integrated circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8004779A
Other languages
Japanese (ja)
Inventor
Satoshi Aihara
Kazuyuki Kawachi
Yoichi Arita
Shoji Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8004779A priority Critical patent/JPS564265A/en
Publication of JPS564265A publication Critical patent/JPS564265A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To eliminate the detour of a wire in a semiconductor integrated circuit device adapted for an automatic wiring by so arranging a plurality of cells in a checkered pattern as to be displaced with each other on a chip when laying out the cells with a master slice method. CONSTITUTION:When ICs are laid out on a chip with a master slice method, respective cells CEL are so arranged in a checkered pattern as to be displaced with each other. That is, when respective cells CELa and CELb are arranged on a chip having input and output terminals i and o as well as wiring area Ocon, they are aligned in checkered pattern to be displaced with each other. In this manner, the wires for connecting the input and output terminals i and o of these cells may include Y- direction wires y1, y2 of first layer and X-direction wires x1, x2 of second layer to be inclusive only four wires so as to reduce the number of wiring channels and to also eliminate the conflict of these wires each other.
JP8004779A 1979-06-25 1979-06-25 Semiconductor integrated circuit device Pending JPS564265A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8004779A JPS564265A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8004779A JPS564265A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS564265A true JPS564265A (en) 1981-01-17

Family

ID=13707320

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8004779A Pending JPS564265A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS564265A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196557A (en) * 1981-05-27 1982-12-02 Nec Corp Semiconductor device
JPS595646A (en) * 1982-07-01 1984-01-12 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57196557A (en) * 1981-05-27 1982-12-02 Nec Corp Semiconductor device
JPS595646A (en) * 1982-07-01 1984-01-12 Nec Corp Semiconductor device
JPH0236072B2 (en) * 1982-07-01 1990-08-15 Nippon Electric Co

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