JPS564264A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS564264A
JPS564264A JP8004679A JP8004679A JPS564264A JP S564264 A JPS564264 A JP S564264A JP 8004679 A JP8004679 A JP 8004679A JP 8004679 A JP8004679 A JP 8004679A JP S564264 A JPS564264 A JP S564264A
Authority
JP
Japan
Prior art keywords
terminals
directions
led out
cells
wires
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8004679A
Other languages
Japanese (ja)
Inventor
Satoshi Aihara
Kazuyuki Kawachi
Yoichi Arita
Shoji Sato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8004679A priority Critical patent/JPS564264A/en
Publication of JPS564264A publication Critical patent/JPS564264A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H01L27/11801—Masterslice integrated circuits using bipolar technology

Abstract

PURPOSE:To enhance the wiring rate of a semiconductor integrated circuit device and increase the freedom degree of wires thereof by arranging cell signal leading terminals obliquely with respect to X and Y directions when forming a plurality of cells with a master slice method. CONSTITUTION:When terminals T are provided at respective cells CEL forming an IC, the terminals T are not arranged in a linear line but obliquely. That is, signal wires are led out in both directions from an X point as a center and are further led out in both directions from a Y point as a center to be thus led out totally in four directions so as to be easily led out therefrom. When a plurality of such cells CEL are arranged on a semiconductor substrate, the cells CEL are aligned in checkered pattern in such a manner that te input and output terminals Ti11-Ti21 and Tot1- Tot2 of the respective cells are arranged obliquely in the internal wiring areas Ocon1-Ocon2. Since the respective terminals are displaced in this manner, they do not disturb each other when leading out the signal wires therefrom, but the wires may be arranged linearly so as to be easily laid out.
JP8004679A 1979-06-25 1979-06-25 Semiconductor integrated circuit device Pending JPS564264A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8004679A JPS564264A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8004679A JPS564264A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS564264A true JPS564264A (en) 1981-01-17

Family

ID=13707292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8004679A Pending JPS564264A (en) 1979-06-25 1979-06-25 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS564264A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045348A (en) * 1983-08-22 1985-03-11 馬渕　健一 Beating tool
JPS6048745A (en) * 1983-08-24 1985-03-16 馬渕　健一 Beating tool
JPS6048746A (en) * 1983-08-24 1985-03-16 馬渕　健一 Beating tool

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6045348A (en) * 1983-08-22 1985-03-11 馬渕　健一 Beating tool
JPH0328219B2 (en) * 1983-08-22 1991-04-18 Kenichi Mabuchi
JPS6048745A (en) * 1983-08-24 1985-03-16 馬渕　健一 Beating tool
JPS6048746A (en) * 1983-08-24 1985-03-16 馬渕　健一 Beating tool
JPH0348824B2 (en) * 1983-08-24 1991-07-25 Kenichi Mabuchi
JPH0348825B2 (en) * 1983-08-24 1991-07-25 Kenichi Mabuchi

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