JPS5739553A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5739553A
JPS5739553A JP55115186A JP11518680A JPS5739553A JP S5739553 A JPS5739553 A JP S5739553A JP 55115186 A JP55115186 A JP 55115186A JP 11518680 A JP11518680 A JP 11518680A JP S5739553 A JPS5739553 A JP S5739553A
Authority
JP
Japan
Prior art keywords
wiring
pattern
pads
external terminal
terminal groups
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP55115186A
Other languages
Japanese (ja)
Inventor
Tsuyoshi Sanada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP55115186A priority Critical patent/JPS5739553A/en
Publication of JPS5739553A publication Critical patent/JPS5739553A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To standardize a semiconductor device and to eliminate the error in the wiring pattern of the device by forming in advance the wiring pattern secured on a substrate in the midway of the wire which connects an input/output level converter to an internal logic circuit in the peripheral pattern of complicated shape. CONSTITUTION:Input converters 41, 42 and output transistor 51 are respectively formed at a ratio of 1:1/2 at terminal pads 21, 22, and virtual external terminal groups 71, 72, 73 disposed at the end of a wiring channel and virtual external terminal groups 74, 75, 76 are respectively corresponded to pads 21 and 22. Wiring pattern pads 21, 22 which connect the virtual external terminal groups corresponding to the respective pads are prepared in advance with stationary wires 81, 82 corresponding thereto. Patterns 91, 92 are inhibited in wiring due to complicated pattern shape. In this manner, a program due to the design automation can be facilitated, and the error in the pattern can be eliminated, thereby standardizing and simplifying the wiring shape.
JP55115186A 1980-08-21 1980-08-21 Semiconductor device Pending JPS5739553A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55115186A JPS5739553A (en) 1980-08-21 1980-08-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55115186A JPS5739553A (en) 1980-08-21 1980-08-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5739553A true JPS5739553A (en) 1982-03-04

Family

ID=14656480

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55115186A Pending JPS5739553A (en) 1980-08-21 1980-08-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5739553A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02216850A (en) * 1990-01-29 1990-08-29 Hitachi Ltd Semiconductor integrated circuit device
US5512847A (en) * 1983-01-31 1996-04-30 Hitachi, Ltd. BiCMOS tri-state output driver

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5512847A (en) * 1983-01-31 1996-04-30 Hitachi, Ltd. BiCMOS tri-state output driver
JPH02216850A (en) * 1990-01-29 1990-08-29 Hitachi Ltd Semiconductor integrated circuit device

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