JPS57112048A - Master slice type semiconductor integrated circuit device - Google Patents

Master slice type semiconductor integrated circuit device

Info

Publication number
JPS57112048A
JPS57112048A JP18725180A JP18725180A JPS57112048A JP S57112048 A JPS57112048 A JP S57112048A JP 18725180 A JP18725180 A JP 18725180A JP 18725180 A JP18725180 A JP 18725180A JP S57112048 A JPS57112048 A JP S57112048A
Authority
JP
Japan
Prior art keywords
wiring
region
surround
master slice
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18725180A
Other languages
Japanese (ja)
Inventor
Yoshihide Sugiura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18725180A priority Critical patent/JPS57112048A/en
Publication of JPS57112048A publication Critical patent/JPS57112048A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Abstract

PURPOSE:To reduce ratio of occupied area of clock wiring by a method wherein a clock distributing line which is used to test FF circuits built in a master slice IC is constructed to form a number of clock signal feeding terminals that surround main circuit formation region, and a most available FF circuit is connected by wiring. CONSTITUTION:An I/O buffer cell 6 is arranged so as to surround the circumference of a main circuit formation region 5 in which various gates that are main parts of a master slice IC are arranged. In this constitution A wiring 7 which passes through the cell is formed using an excessive region in the cell 6, and the wiring 7 is used as a wiring that surround main circuit formation region 5. And at the corners a corner pattern 8 is provided so as to surround the region 5 annularly. By this constitution the FF circuit 1 and the wiring 7 are connected using a wiring 10 after a most available terminal is selected. By this method the occupied region by the clock wiring is reduced in a wiring region 11.
JP18725180A 1980-12-29 1980-12-29 Master slice type semiconductor integrated circuit device Pending JPS57112048A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18725180A JPS57112048A (en) 1980-12-29 1980-12-29 Master slice type semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18725180A JPS57112048A (en) 1980-12-29 1980-12-29 Master slice type semiconductor integrated circuit device

Publications (1)

Publication Number Publication Date
JPS57112048A true JPS57112048A (en) 1982-07-12

Family

ID=16202687

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18725180A Pending JPS57112048A (en) 1980-12-29 1980-12-29 Master slice type semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS57112048A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257543A (en) * 1984-06-04 1985-12-19 Toshiba Corp Synchronizing signal supplying circuit in semiconductor integrated circuit
JPS613430A (en) * 1984-06-15 1986-01-09 Nec Corp Semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60257543A (en) * 1984-06-04 1985-12-19 Toshiba Corp Synchronizing signal supplying circuit in semiconductor integrated circuit
JPS613430A (en) * 1984-06-15 1986-01-09 Nec Corp Semiconductor device
JPH0523071B2 (en) * 1984-06-15 1993-03-31 Nippon Electric Co

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