JPS554974A - Layout pattern scanning system - Google Patents

Layout pattern scanning system

Info

Publication number
JPS554974A
JPS554974A JP7788778A JP7788778A JPS554974A JP S554974 A JPS554974 A JP S554974A JP 7788778 A JP7788778 A JP 7788778A JP 7788778 A JP7788778 A JP 7788778A JP S554974 A JPS554974 A JP S554974A
Authority
JP
Japan
Prior art keywords
scanning
coordinate values
layout pattern
mask range
pattern
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7788778A
Other languages
Japanese (ja)
Inventor
Mamoru Iwatsuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP7788778A priority Critical patent/JPS554974A/en
Publication of JPS554974A publication Critical patent/JPS554974A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: For cutting down the time required for scanning and raising scanning accuracy, to automate the scanning of the layout patterns of IC's and LST's by using a computer.
CONSTITUTION: A layout pattern 11 is read out by a coordinate reader 12, and the coordinate values at the tops of the polygons each forming one section of a pattern are coded by a coding means 13 and put one upon another. Next, this processing is made repeatedly for all sections. The input of the relation of logical connections from a data input means 14 and that of the coordinate values obtained by said means 13 are identified by a junction relation identifying means 15, and inefinite, doubtful and erroneous matters and indicated by an indicating means 16. Thus, it is checked whether the connections of a metallic wiring layer 1, a diffusion layer 2, a gate mask range 3, a contact mask range 4, an output signal terminal 6, an output terminal 7, a power supply wiring 9 and an NOT circuit 10 may be good.
COPYRIGHT: (C)1980,JPO&Japio
JP7788778A 1978-06-26 1978-06-26 Layout pattern scanning system Pending JPS554974A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7788778A JPS554974A (en) 1978-06-26 1978-06-26 Layout pattern scanning system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7788778A JPS554974A (en) 1978-06-26 1978-06-26 Layout pattern scanning system

Publications (1)

Publication Number Publication Date
JPS554974A true JPS554974A (en) 1980-01-14

Family

ID=13646576

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7788778A Pending JPS554974A (en) 1978-06-26 1978-06-26 Layout pattern scanning system

Country Status (1)

Country Link
JP (1) JPS554974A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052438U (en) * 1983-09-20 1985-04-12 トキコ株式会社 hydraulic shock absorber
US4907465A (en) * 1986-11-10 1990-03-13 Kubota Ltd. Change speed control structure for hydraulic transmission

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052438U (en) * 1983-09-20 1985-04-12 トキコ株式会社 hydraulic shock absorber
JPH025135Y2 (en) * 1983-09-20 1990-02-07
US4907465A (en) * 1986-11-10 1990-03-13 Kubota Ltd. Change speed control structure for hydraulic transmission

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