JPS5715440A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS5715440A JPS5715440A JP9090180A JP9090180A JPS5715440A JP S5715440 A JPS5715440 A JP S5715440A JP 9090180 A JP9090180 A JP 9090180A JP 9090180 A JP9090180 A JP 9090180A JP S5715440 A JPS5715440 A JP S5715440A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- terminals
- pattern
- block
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title 1
- 238000010586 diagram Methods 0.000 abstract 1
- 238000004904 shortening Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To enable a wiring layout by complete DA processing by arranging several connection terminals at the terminals of a basic logic at operation circuit pattern formeed in a block in a circuit device of a master slicing system. CONSTITUTION:For example, a logical operation circuit 100 with 3 inputs and 2 outputs comprising a 2-output OR circuit, a 1-input level shift circuit and 2-output exclusive NOR/OR circuit is formed in a specified block. As shown by the block symbol diagram, a pattern is so arranged at the inputs and outputs of the circuit that equivalent terminals 6 and 7 are provided for at least one of the terminals such as output terminal 4 connected to wiring channels 101-120 to make an available lattice point. A block pattern may be arranged with several connecting points provided at each input/output terminal. This can increase the freedom of connection so much that the layout of the connection wiring pattern can be performed by sepcified DA processing thereby shortening the designing time and preventing possible miswiring.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9090180A JPS5715440A (en) | 1980-07-03 | 1980-07-03 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9090180A JPS5715440A (en) | 1980-07-03 | 1980-07-03 | Semiconductor device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5715440A true JPS5715440A (en) | 1982-01-26 |
JPH0127580B2 JPH0127580B2 (en) | 1989-05-30 |
Family
ID=14011294
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9090180A Granted JPS5715440A (en) | 1980-07-03 | 1980-07-03 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5715440A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0232044A2 (en) * | 1986-02-06 | 1987-08-12 | Nortel Networks Corporation | Integrated circuit chip having a plurality of integrated circuit cells |
EP0288688A2 (en) * | 1987-04-30 | 1988-11-02 | International Business Machines Corporation | Porous circuit macro for semiconductor integrated circuits |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50154079A (en) * | 1974-05-31 | 1975-12-11 | ||
JPS5387A (en) * | 1976-06-24 | 1978-01-05 | Toshiba Corp | Automatic design system |
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JPS5492190A (en) * | 1977-12-29 | 1979-07-21 | Fujitsu Ltd | Integrated circuit |
-
1980
- 1980-07-03 JP JP9090180A patent/JPS5715440A/en active Granted
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS50154079A (en) * | 1974-05-31 | 1975-12-11 | ||
JPS5387A (en) * | 1976-06-24 | 1978-01-05 | Toshiba Corp | Automatic design system |
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
JPS5492190A (en) * | 1977-12-29 | 1979-07-21 | Fujitsu Ltd | Integrated circuit |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0232044A2 (en) * | 1986-02-06 | 1987-08-12 | Nortel Networks Corporation | Integrated circuit chip having a plurality of integrated circuit cells |
EP0288688A2 (en) * | 1987-04-30 | 1988-11-02 | International Business Machines Corporation | Porous circuit macro for semiconductor integrated circuits |
Also Published As
Publication number | Publication date |
---|---|
JPH0127580B2 (en) | 1989-05-30 |
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