JPS5492190A - Integrated circuit - Google Patents
Integrated circuitInfo
- Publication number
- JPS5492190A JPS5492190A JP15948377A JP15948377A JPS5492190A JP S5492190 A JPS5492190 A JP S5492190A JP 15948377 A JP15948377 A JP 15948377A JP 15948377 A JP15948377 A JP 15948377A JP S5492190 A JPS5492190 A JP S5492190A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- lsi
- theoretical
- length
- greatly shortened
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000010365 information processing Effects 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To provide a plural number of lead-out terminals for inputs and outputs of the theoretical blocks that from an LSI, so that the length of wiring between theoretical blocks of the LSI can be greatly shortened and the wiring area can be reduced. CONSTITUTION:A plural number of, say, 2 lead-out termals are provide for the inputs and outputs of theoretical block 2 which form an LSI. With this arrangement, the length of wiring at wiring area 4 can be greatly shortened. With the arrangement, the length of wiring between theoretical blocks of the LSI can be greatly shortened, resulting in improvement in the performance of the information processing unit and in reduction of the wiring area.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15948377A JPS5492190A (en) | 1977-12-29 | 1977-12-29 | Integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15948377A JPS5492190A (en) | 1977-12-29 | 1977-12-29 | Integrated circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5492190A true JPS5492190A (en) | 1979-07-21 |
Family
ID=15694746
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15948377A Pending JPS5492190A (en) | 1977-12-29 | 1977-12-29 | Integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5492190A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5715440A (en) * | 1980-07-03 | 1982-01-26 | Nec Corp | Semiconductor device |
JPS57199239A (en) * | 1981-06-02 | 1982-12-07 | Nec Corp | Semiconductor integrated circuit device |
JPS5887854A (en) * | 1981-11-20 | 1983-05-25 | Nec Corp | Master slice system lsi substrate |
JPS63199443A (en) * | 1987-02-16 | 1988-08-17 | Toshiba Corp | Setting method for position of terminal for building block including poly cell block |
EP0288688A2 (en) * | 1987-04-30 | 1988-11-02 | International Business Machines Corporation | Porous circuit macro for semiconductor integrated circuits |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1977
- 1977-12-29 JP JP15948377A patent/JPS5492190A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5715440A (en) * | 1980-07-03 | 1982-01-26 | Nec Corp | Semiconductor device |
JPH0127580B2 (en) * | 1980-07-03 | 1989-05-30 | Nippon Electric Co | |
JPS57199239A (en) * | 1981-06-02 | 1982-12-07 | Nec Corp | Semiconductor integrated circuit device |
JPS5887854A (en) * | 1981-11-20 | 1983-05-25 | Nec Corp | Master slice system lsi substrate |
JPS63199443A (en) * | 1987-02-16 | 1988-08-17 | Toshiba Corp | Setting method for position of terminal for building block including poly cell block |
EP0288688A2 (en) * | 1987-04-30 | 1988-11-02 | International Business Machines Corporation | Porous circuit macro for semiconductor integrated circuits |
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