JPS5617036A - Semiconductor device - Google Patents

Abstract

PURPOSE:To contrive the improvement in the integrity and the yield of a semiconductor device by forming a delay time extending metallic layer partly at a connecting wire between an input level converter circuit and a logic circuit on a semiconductor substrate. CONSTITUTION:Since delay time difference of the pattern configuration of a functional circuit having a plurality of inputs equal at delay time for inputting to an internal logic circuit 73 through an internal drive input circuit 12 is proportional to the product of the difference between the input circuit 12 and the logic circuit 73 in wiring capacity and the output resistance of the input circuit, when there is provided a distance corresponding to the difference between the wires in the capacity is provided on the output wire 13 of the input circuit 12 (or as branched with the wire) in the vicinity of the input circuit 12 at the side of short delay time, the balance of the delay time can be easily controlled on the pattern. Accordingly, it does not deteriorate the integrity of the semiconductor device nor complicate the shape of the other wires in matching with the wiring length of the terminal having maximum time constant, not necessitate the selective expansion of the wiring width so as to prevent erroneous pattern.