JPS55165668A - Semiconductor integrated circuit device - Google Patents

Semiconductor integrated circuit device

Info

Publication number
JPS55165668A
JPS55165668A JP7336779A JP7336779A JPS55165668A JP S55165668 A JPS55165668 A JP S55165668A JP 7336779 A JP7336779 A JP 7336779A JP 7336779 A JP7336779 A JP 7336779A JP S55165668 A JPS55165668 A JP S55165668A
Authority
JP
Japan
Prior art keywords
cells
cell
adjacent
cel14
lsi
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7336779A
Other languages
Japanese (ja)
Other versions
JPS6358372B2 (en
Inventor
Shigenori Baba
Hideo Kikuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP7336779A priority Critical patent/JPS55165668A/en
Publication of JPS55165668A publication Critical patent/JPS55165668A/en
Publication of JPS6358372B2 publication Critical patent/JPS6358372B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/118—Masterslice integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce the chip size by forming cut parts in the opposite edges of adjacent cells and by providing the input-output terminals there when plural cells each of which is a unit element or unit circuit are arranged on making themselves adjacent to each other to form an LSI. CONSTITUTION:The cells CEL11-CEL14 each of which is a unit element or unit circuit are arranged on making themselves adjacent to each other to form an LSI of the building block master slice system. In this case, the cut parts CT which are opposite to ones of adjacent cells are shaped in each cell, the input-output terminals TM are provided inside of the cut part CT and the terminal TM is not projected to the outside of the cell. After this, these cells CEL11-CEL14 are closely arranged, and the cells CEL12 and CEL13 are connected to each other with the wiring L4 through the terminal TM as required. Also the wiring L2 is installed on the outside of the cell to connect the cells that are separated from each other. In this way, since the connection is possible in the cut part, the occupied area can be reduced.
JP7336779A 1979-06-11 1979-06-11 Semiconductor integrated circuit device Granted JPS55165668A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7336779A JPS55165668A (en) 1979-06-11 1979-06-11 Semiconductor integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7336779A JPS55165668A (en) 1979-06-11 1979-06-11 Semiconductor integrated circuit device

Publications (2)

Publication Number Publication Date
JPS55165668A true JPS55165668A (en) 1980-12-24
JPS6358372B2 JPS6358372B2 (en) 1988-11-15

Family

ID=13516129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7336779A Granted JPS55165668A (en) 1979-06-11 1979-06-11 Semiconductor integrated circuit device

Country Status (1)

Country Link
JP (1) JPS55165668A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594151A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor circuit with building block structure
DE102007001196A1 (en) * 2007-01-05 2008-07-10 Infineon Technologies Ag Integrated circuit's layout designing method, involves providing cells, where maximum expansions of cells are equal in direction, and placing cells for providing layout of integrated circuit, where external boundary line has form of polygon
DE102007063765B3 (en) * 2007-01-05 2013-02-07 Infineon Technologies Ag Integrated circuit's layout designing method, involves providing cells, where maximum expansions of cells are equal in direction, and placing cells for providing layout of integrated circuit, where external boundary line has form of polygon

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01137483A (en) * 1987-11-24 1989-05-30 Nec Corp Magnetic head assembly
CA1313261C (en) * 1988-03-23 1993-01-26 Digital Equipment Corporation Low profile head-load beam slider arm for disk drive

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS594151A (en) * 1982-06-30 1984-01-10 Fujitsu Ltd Semiconductor circuit with building block structure
DE102007001196A1 (en) * 2007-01-05 2008-07-10 Infineon Technologies Ag Integrated circuit's layout designing method, involves providing cells, where maximum expansions of cells are equal in direction, and placing cells for providing layout of integrated circuit, where external boundary line has form of polygon
US7979828B2 (en) 2007-01-05 2011-07-12 Infineon Technologies Ag Integrated circuit and method for determining an integrated circuit layout
DE102007001196B4 (en) * 2007-01-05 2012-01-05 Infineon Technologies Ag A method of designing the layout of an integrated circuit and associated integrated circuit
DE102007063765B3 (en) * 2007-01-05 2013-02-07 Infineon Technologies Ag Integrated circuit's layout designing method, involves providing cells, where maximum expansions of cells are equal in direction, and placing cells for providing layout of integrated circuit, where external boundary line has form of polygon

Also Published As

Publication number Publication date
JPS6358372B2 (en) 1988-11-15

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