JPS57184226A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS57184226A
JPS57184226A JP56069010A JP6901081A JPS57184226A JP S57184226 A JPS57184226 A JP S57184226A JP 56069010 A JP56069010 A JP 56069010A JP 6901081 A JP6901081 A JP 6901081A JP S57184226 A JPS57184226 A JP S57184226A
Authority
JP
Japan
Prior art keywords
bumps
leads
chip
noses
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56069010A
Other languages
Japanese (ja)
Inventor
Takashi Miyamoto
Soichi Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP56069010A priority Critical patent/JPS57184226A/en
Publication of JPS57184226A publication Critical patent/JPS57184226A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01082Lead [Pb]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/15165Monolayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To prevent a voltage drop by connecting one lead to both bumps by forming the bumps to the outer edge section and central section of a chip in internal wiring, in which the voltage drop is at issue, in the semiconductor device assembled through a gang-bonding system. CONSTITUTION:The bumps 2a', 2b' are shaped onto the power supply lines 3a, 3b of a lead frame, and leads 4a, 4b corresponding to bumps 2a, 2b are lengthened and the noses are each connected to the bumps 2a', 2b'. Accordingly, voltage at the bumps 2a', 2b' is approximately the same as the bumps 2a, 2b. Connecting property with the bumps 2a', 2b' is also improved when the noses of the leads 4a, 4b are thined previously. There is no danger that a short circuit is generated due to the hanging of the leads and the contact with the edge of the chip of the leads because the leads 4a, 4b are also connected to the bumps 2a, 2b of the outer edge section of the chip.
JP56069010A 1981-05-08 1981-05-08 Semiconductor device Pending JPS57184226A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56069010A JPS57184226A (en) 1981-05-08 1981-05-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56069010A JPS57184226A (en) 1981-05-08 1981-05-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS57184226A true JPS57184226A (en) 1982-11-12

Family

ID=13390187

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56069010A Pending JPS57184226A (en) 1981-05-08 1981-05-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS57184226A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161738A (en) * 1988-12-15 1990-06-21 Hitachi Cable Ltd Tape carrier for tab
WO1996010841A1 (en) * 1994-09-30 1996-04-11 Vlsi Technology, Inc. Global signal net
JP2010103535A (en) * 2008-10-23 2010-05-06 Samsung Electronics Co Ltd Semiconductor package

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5284969A (en) * 1976-01-07 1977-07-14 Hitachi Ltd Electrode connection method and lead tape used for the same
JPS53139976A (en) * 1977-05-13 1978-12-06 Seiko Epson Corp Packaging method of semiconductor chips
JPS54133878A (en) * 1978-04-07 1979-10-17 Nec Corp Semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5284969A (en) * 1976-01-07 1977-07-14 Hitachi Ltd Electrode connection method and lead tape used for the same
JPS53139976A (en) * 1977-05-13 1978-12-06 Seiko Epson Corp Packaging method of semiconductor chips
JPS54133878A (en) * 1978-04-07 1979-10-17 Nec Corp Semiconductor device

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02161738A (en) * 1988-12-15 1990-06-21 Hitachi Cable Ltd Tape carrier for tab
JPH0586065B2 (en) * 1988-12-15 1993-12-09 Hitachi Cable
WO1996010841A1 (en) * 1994-09-30 1996-04-11 Vlsi Technology, Inc. Global signal net
JP2010103535A (en) * 2008-10-23 2010-05-06 Samsung Electronics Co Ltd Semiconductor package

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