JPS5375760A - Manufacture for semiconductor device - Google Patents

Manufacture for semiconductor device

Info

Publication number
JPS5375760A
JPS5375760A JP15152876A JP15152876A JPS5375760A JP S5375760 A JPS5375760 A JP S5375760A JP 15152876 A JP15152876 A JP 15152876A JP 15152876 A JP15152876 A JP 15152876A JP S5375760 A JPS5375760 A JP S5375760A
Authority
JP
Japan
Prior art keywords
manufacture
semiconductor device
stabling
suppressing
current supply
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15152876A
Other languages
Japanese (ja)
Inventor
Masaru Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15152876A priority Critical patent/JPS5375760A/en
Publication of JPS5375760A publication Critical patent/JPS5375760A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods

Landscapes

  • Electrodes Of Semiconductors (AREA)

Abstract

PURPOSE: To manufacture the thick terminal wiring of designed size, by suppressing the plating side surface widening and by stabling the current supply distribution.
COPYRIGHT: (C)1978,JPO&Japio
JP15152876A 1976-12-16 1976-12-16 Manufacture for semiconductor device Pending JPS5375760A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15152876A JPS5375760A (en) 1976-12-16 1976-12-16 Manufacture for semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15152876A JPS5375760A (en) 1976-12-16 1976-12-16 Manufacture for semiconductor device

Publications (1)

Publication Number Publication Date
JPS5375760A true JPS5375760A (en) 1978-07-05

Family

ID=15520474

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15152876A Pending JPS5375760A (en) 1976-12-16 1976-12-16 Manufacture for semiconductor device

Country Status (1)

Country Link
JP (1) JPS5375760A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043440A (en) * 2000-06-30 2002-02-08 Hynix Semiconductor Inc Semiconductor memory and its manufacturing method
JP2010098139A (en) * 2008-10-16 2010-04-30 Fuji Electric Systems Co Ltd Semiconductor device manufacturing method
JP2010182807A (en) * 2009-02-04 2010-08-19 Fuji Electric Systems Co Ltd Method of manufacturing semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002043440A (en) * 2000-06-30 2002-02-08 Hynix Semiconductor Inc Semiconductor memory and its manufacturing method
JP2010098139A (en) * 2008-10-16 2010-04-30 Fuji Electric Systems Co Ltd Semiconductor device manufacturing method
JP2010182807A (en) * 2009-02-04 2010-08-19 Fuji Electric Systems Co Ltd Method of manufacturing semiconductor device

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