JPS5797637A - Substrate for test of semiconductor chip - Google Patents

Substrate for test of semiconductor chip

Info

Publication number
JPS5797637A
JPS5797637A JP17320380A JP17320380A JPS5797637A JP S5797637 A JPS5797637 A JP S5797637A JP 17320380 A JP17320380 A JP 17320380A JP 17320380 A JP17320380 A JP 17320380A JP S5797637 A JPS5797637 A JP S5797637A
Authority
JP
Japan
Prior art keywords
substrate
size
earth layer
conductors
characteristic impedance
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17320380A
Other languages
Japanese (ja)
Other versions
JPS6234144B2 (en
Inventor
Fumiyuki Kobayashi
Katsumi Yabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP17320380A priority Critical patent/JPS5797637A/en
Publication of JPS5797637A publication Critical patent/JPS5797637A/en
Publication of JPS6234144B2 publication Critical patent/JPS6234144B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor

Abstract

PURPOSE:To make characteristic impedance on the substrate side of a substrate for test of semiconductor chip to match the characteristic impedance on the cable side by a method wherein size of wirings from input/output terminals up to reach a pedestal layer on the surface of the substrate, size of an earth layer on the back of the substrate, permittivity of the substrate material, etc., are selected. CONSTITUTION:Corresponding to bumps provided in a lattice type at the center part of a chip, individual pedestal 4 is formed in the lattice type the same on the heat resistance glass substrate 3, pads 6 are arranged in order at the end parts of the substrate 3, and a pattern 5 to connect the pads 6 and the pedestals 4 by one to one is arranged. Microstrip lines are formed by the earth layer formed on the back of the glass substrate 3 and the conductors formed on the surface, and characteristic impedance on the substrate side can be regulated by the size of the conductors, size of the earth layer, the distance from the conductors up to the earth layer, permittivity of the glass substrate, etc.
JP17320380A 1980-12-10 1980-12-10 Substrate for test of semiconductor chip Granted JPS5797637A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17320380A JPS5797637A (en) 1980-12-10 1980-12-10 Substrate for test of semiconductor chip

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17320380A JPS5797637A (en) 1980-12-10 1980-12-10 Substrate for test of semiconductor chip

Publications (2)

Publication Number Publication Date
JPS5797637A true JPS5797637A (en) 1982-06-17
JPS6234144B2 JPS6234144B2 (en) 1987-07-24

Family

ID=15956016

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17320380A Granted JPS5797637A (en) 1980-12-10 1980-12-10 Substrate for test of semiconductor chip

Country Status (1)

Country Link
JP (1) JPS5797637A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481333A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Test board for flip-chip
EP1930941A2 (en) * 2006-11-15 2008-06-11 AirDio Wireless Inc. Method of chip manufacturing

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6481333A (en) * 1987-09-24 1989-03-27 Hitachi Ltd Test board for flip-chip
EP1930941A2 (en) * 2006-11-15 2008-06-11 AirDio Wireless Inc. Method of chip manufacturing
EP1930941A3 (en) * 2006-11-15 2008-08-20 AirDio Wireless Inc. Method of chip manufacturing

Also Published As

Publication number Publication date
JPS6234144B2 (en) 1987-07-24

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