JPS6234144B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor chip test substrate suitable for use in testing semiconductor chips, particularly flip-chip semiconductor devices.

Conventionally, in testing semiconductor devices, a DC characteristic test is performed at the wafer stage, and chips obtained from wafers that are determined to be good in this test are bonded to a package that meets the purpose using a wire bonding method, etc. For example, tests were performed at the chip stage after being housed in a dual in-line package or flat package. Therefore, when testing the direct current and alternating current characteristics of a single chip, the package was supported by a station jig that matched the shape of the package, and the chip could be easily tested through the input/output leads of the package.
However, in recent years, due to the demand for high performance and high integration,
With the advent of hybrid technology, hybrid multi-chip packages have come into use. At that time, a commonly used bonding method is CCB (Controlled Collapse Bonding).
There is a flip-chip bonding method called.
As is well known, CCB is a face-down bonding technology in which solder balls 2 called bumps are provided on a semiconductor chip 1 and attached to a pedestal part of a ceramic substrate (not shown) using a solder reflow method, as shown in Figure 1. . Therefore, when testing each semiconductor chip employing the CCB method before mounting it on a ceramic substrate or the like, it is necessary to accurately position each chip and bring the prober connected to the tester into contact with the bumps 2. However, as the operation speed of semiconductor devices increases, AC characteristic tests require that there be no mismatched characteristic impedances in the entire test system consisting of chips, probers, testers, etc. Therefore, the probers and the like require finely shaped probers in accordance with the miniaturization of the bump arrangement on semiconductor chips, but it is necessary to provide a uniform characteristic impedance to each of the plurality of probers required for each bump. It is extremely difficult to make it last.

Therefore, testing individual chips with a prober,
In particular, the AC characteristic test is inconvenient from the viewpoint of the above-mentioned characteristic impedance.

In addition, a ceramic wiring board (hereinafter referred to as a chip carrier) with test terminals installed in the front was used.
There is also a method of mounting each chip individually and testing through test terminals, but when separating the solder joints connecting the chip and the chip carrier after the test, there is a possibility that the semiconductor chip may be damaged in the initial stage. The amount of solder was lost to the chip carrier,
It becomes impossible to maintain a uniform amount of solder on the bumps on the chip. Moreover, the shape, height, volume, etc. of the bump are extremely closely related to the reliability of the CCB method.

Therefore, there was an inconvenience that the bumps had to be regenerated after the chip was removed. Furthermore, as semiconductor devices become more highly integrated, the number of input/output terminals also increases. This is well known empirically as Lent's law, and the following relational expression holds between the number P of input/output terminals and the number G of gates.

P=kG〓 Here, k and γ are constants.For example, in a semiconductor chip with a degree of integration of 700 gates, approximately 140 input/output terminals are required. Providing a large number of bumps corresponding to such a large number of input/output terminals on only the four sides of a chip of several millimeters square is not only difficult in manufacturing and assembly, but also causes problems in wiring design of semiconductor devices and problems with fine bump sizes. However, there are problems with reliability and other issues associated with this process. Therefore, it is necessary to arrange the bumps in a matrix in the center of the chip instead of on the four sides of the chip. For example, the grid spacing is set to 0.25 mm, and bumps are formed and arranged at each (12 x 12) grid point. The need arises. Also, when testing a chip with bumps in a matrix like this, it is necessary to ensure that each bump on the chip side contacts each pedestal on the substrate side, but as mentioned above, the CCB method Since this is a face-down bonding technology in which the surface is directed toward the substrate to be bonded, it is possible to visually align the bumps and pedestals using a half mirror, etc., if only the four sides of the chip are used. In the central part, there is no way to check the contact status between the bump and the pedestal, so even if a test result shows a defect, it is difficult to determine whether it is due to a defect in the chip itself or a poor contact between the bump and the pedestal. There is an inconvenience. Therefore, testing methods using chip carriers using ceramic substrates still have disadvantages. Furthermore, in the method using the prober mentioned above, it is technically difficult to bring the prober into contact with each of the many bumps arranged in a grid in the center of the chip, let alone to make the characteristic impedance of each prober the same. .

The present invention has been made in view of the above-mentioned conventional technical circumstances, and therefore, an object of the present invention is to solve the problem of mismatching of characteristic impedances to enable AC characteristic testing, and to It is an object of the present invention to provide a substrate for semiconductor chip testing, in which alignment of a grid-like bump section arranged in the center and a pedestal section on the substrate side can be easily and visually performed.

The key point of the configuration of the present invention is that on the surface of a transparent glass substrate, etc., input/output terminals are provided at the periphery, and a pedestal layer is provided at the center corresponding to the arrangement of input/output bumps on the semiconductor chip to be tested. In addition to wiring each input/output terminal and each pedestal layer, a ground layer is provided on the back side of the board at the periphery except for the center part, and when positioning the bumps of the chip to be tested on the pedestal layer. The test can be performed visually using optical means from the back side of the central part of the transparent board, and the signal line of the coaxial cable leading to the tester is connected to the input/output terminal on the periphery of the board surface. Connect the ground wire to the ground layer on the back side of the board. At this time, check the shape and size of the wiring from the input/output terminal on the front side of the board to the pedestal layer, the shape and size of the ground layer on the back side of the board, the dielectric constant of the board material, etc. as appropriate. By selecting , it is possible to match the characteristic impedance of the board side to that of the cable side.

Next, one embodiment of the present invention will be described in detail with reference to the drawings.

FIG. 2 is a top view showing an embodiment of the present invention;
FIG. 3 is a side view of the same.

Please refer to FIGS. 2 and 3.

A transparent substrate with heat resistance and flatness, for example, a square heat-resistant glass substrate 3 with a length of about 20 mm and a width of about 30 mm.
On the top, individual pedestals 4 are arranged in a grid pattern in correspondence with the bumps arranged in a grid pattern in the center of the chip to be tested (not shown) (here, to simplify the drawing). For this reason, we will show an example of how to correspond to 16 bumps on the chip)
Further, at the end of the substrate 3, a pattern 5 for arranging the pads 6 and connecting the pads 6 and the pedestal 4 in a one-to-one manner is arranged, but this can be done using a known technique. I can do it. For example, board 3
Since this is a flat glass substrate, well-known thin film technology can be easily used to form the pad 6, pedestal 4, pattern 5, etc. That is, the conductor pattern can be formed by mask deposition using the most common vacuum deposition method, or by photoetching technology. Specifically aluminum
A metal with good adhesive properties, such as Al or chromium Cr, is deposited as a first layer on a glass substrate, and a metal with good conductivity, such as copper, is deposited on the metal to a thickness of, for example, about 5 to 10 μm. If necessary, one method is to deposit copper Cu using a plating method after depositing a thin first layer. Thereafter, gold (Au) is deposited on the portions to be left as conductors using a mask evaporation method. Furthermore, a desired circuit pattern is formed using a well-known photoresist technique. In the series of steps described above, it is preferable to provide the ground conductive layer 7 on the back surface of the glass substrate 3 at the same time. A microstrip line is formed by the conductor formed on the front surface of the glass substrate 3 and the ground layer formed on the back surface, so the dimensions such as the width of the conductor, the dimensions of the ground layer, and the distance from the conductor to the ground layer are , depending on the dielectric constant of the glass substrate, etc.
It is well known that the characteristic impedance on the substrate side can be adjusted.

When forming the ground layer 7 on the back surface of the glass substrate 3, at least the back surface portion corresponding to the grid-shaped portion of the pedestal 4 at the center of the surface should not be covered with the ground layer 7. . And let's call this window 8. In the semiconductor chip testing board thus formed, the signal line of the coaxial cable 9 connected to a tester (not shown) is soldered to the pad 6, and the ground line is connected to the ground layer 7, respectively. It will also be appreciated that the ground pad of the chip to be tested is connected to the ground layer 7 via suitable leads.

The procedure for testing a semiconductor chip mounted by the CCB method using the semiconductor chip testing board according to the present invention constructed as described above will now be described with reference to FIG.

FIG. 4 is an explanatory diagram showing how the test board according to the present invention is used.

In the same figure, the nozzle 21 is a transport means capable of vacuum suctioning and moving the chip 1 to be tested, 30 and 31 are mirrors, 32 is a lens, and 33 is an optical system. .

During the test, first, the chip 1 to be tested is vacuum-suctioned to the nozzle 21, which can be moved in the three-dimensional directions of X, Y, and Z, and the glass substrate 3 is attached to the nozzle 21.
Place the bump 2 on the upper pedestal 4 so that it is accurately positioned. At this time, since the window 8 is transparent, the bumps 2 can be easily detected by an optical system (for example, a microscope) 33, which includes mirrors 30, 31, etc. provided at the bottom of the substrate, and collects the reflected light from these mirrors with a lens 32. It is possible to know the positioning state of the pedestal 4 with respect to the pedestal 4.

Furthermore, better effects can be obtained by connecting this optical system to a television monitor or the like and controlling the nozzle 21 by monitoring this. Chip 1 positioned in this way
By pushing down the nozzle 21 using a suitable drive device (not shown), the bumps (solder balls) 2 of the chip 1 and the pedestals 4 of the substrate 3 are brought into pressure contact. At this time, in order to maintain contact, a stable connection between the chip and the transparent substrate can be obtained by applying pressure to the extent that the bumps are slightly crushed. In addition, there is a chip 1 at the top of the nozzle 21.
It is preferable to provide a spring having an elastic constant sufficient to absorb shock when the solder balls 2 are pressed together and to prevent excessive deformation of the solder balls 2.

As described above, after the chip 1 is fixed to the test substrate according to the present invention and a predetermined test is performed, the chip is moved and stored in a predetermined tray again by the nozzle 21, completing a series of tests.

As explained above, the semiconductor chip test board of the present invention has the advantage that it is possible to effectively conduct not only DC characteristic tests but also AC characteristic tests of semiconductor chips to be mounted by the CCB method. There is.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a chip mounted by the CCB method, Fig. 2 is a top view showing an embodiment of the invention, Fig. 3 is a side view of the same, and Fig. 4 is an embodiment of the invention. FIG. Explanation of symbols, 1... Chip, 2... Bump (solder ball), 3... Glass substrate, 4... Pedestal, 5... Circuit pattern, 6... Input/output terminal (pad), 7... Ground layer , 8... window, 9... coaxial cable, 21... nozzle, 30, 31... mirror, 32... lens, 33... optical system.

Claims (1)

[Claims] 1. On the surface of a substrate made of a transparent material such as glass, there are input/output terminals on the periphery, and a pedestal in the center corresponding to the arrangement of input/output bumps on the semiconductor chip to be tested. In addition to arranging the layers and wiring each input/output terminal and each pedestal layer, a ground layer is provided on the back side of the board at the periphery except for the center part, and during the test, the input/output terminal of the chip to be tested is connected. When positioning and arranging the bumps on the pedestal layer on the substrate surface, it is possible to visually adjust the positioning by optical means from the back side of the substrate through the central transparent substrate part, and When connecting the signal line of the connected cable to the input/output terminal of the board, and the ground point of the cable to the ground layer of the board, check the dielectric constant and thickness of the board material, the dimensions of the ground layer, and from the input/output terminal to the pedestal layer. A board for semiconductor chip testing, characterized in that it is possible to match impedances on the cable side and the board side by adjusting the dimensions of the wiring lines, etc.