JP5306224B2 - Compliance microelectronic assembly and method therefor - Google Patents

Abstract

A method of making a microelectronic assembly includes providing a semiconductor wafer having contacts accessible at a first surface, forming compliant bumps over the first surface and depositing a sacrificial layer over the compliant bumps. The method includes grinding the sacrificial layer and the compliant bumps so as to planarize top surfaces of the compliant bumps, whereby the planarized top surfaces are accessible through said sacrificial layer. The sacrificial layer is removed to expose the compliant bumps and the contacts. A silicone layer is deposited over the compliant bumps and portions of the silicone layer are removed to expose the contacts accessible at the first surface of the semiconductor wafer. Conductive traces are formed having first ends electrically connected with the contacts and second ends overlying the compliant bumps and conductive elements are provided atop the second ends of the traces.

Description

[Cross-reference of related applications]
This application is a MICROELECTRONIC ASSEMBLIES HAVING COMPLIANCE AND METHODS THEREFOR application No. 11/643, filed Dec. 20, 2006, which is incorporated herein by reference. Insist on the profit of No.021. This application is related to US patent application Ser. No. 11 / 360,230, filed Feb. 23, 2006, which is incorporated herein by reference.

[Field of the Invention]
The present invention relates to wafer level semiconductor chip packaging. In particular, the present invention relates to improved compliant wafer and compliant semiconductor package structures and methods for forming the structures.

  Microelectronic devices such as semiconductor chips generally require many input and output connections to other electronic components. The input and output contacts of a semiconductor chip or other equivalent device are typically arranged in a grid pattern that generally covers the surface of the device (commonly referred to as an area array), or each edge on the front of the device Arranged in an elongated row that may extend parallel to the part, adjacent to it or at the center of the front face. In general, a device such as a chip must be physically mounted on a substrate such as a printed circuit board, and the device contacts must be electrically connected to the conductive features of the circuit board. .

  Semiconductor chips are typically provided in packages that facilitate chip handling during manufacturing and mounting of the chip to an external substrate such as a circuit board or other circuit panel. For example, many semiconductor chips are provided in a package suitable for surface mounting. Numerous packages of this general type have been proposed for various applications. Most commonly, such a package includes a dielectric element, commonly referred to as a “chip carrier”, wherein the terminals are formed as metal structures plated or etched on the dielectric. These terminals are typically attached to the chip itself by features such as thin traces that extend along the chip carrier itself, and by thin leads or wires that extend between the chip contacts and the terminals or traces. Connected to contact. In the surface mount process, the package is placed on the circuit board such that each terminal on the package is aligned with a corresponding contact pad on the circuit board. Solder or other bonding material is provided between the terminals and the contact pads. The package can be non-removably bonded in place by heating the assembly to melt or “reflow” the solder or to activate the bonding material.

  Many packages include a solder mass in the form of a solder ball, typically about 0.1 mm to about 0.8 mm (5-30 mils) in diameter, which is attached to the terminals of the package. A package with an array of solder balls protruding from its lower surface is commonly referred to as a ball grid array or “BGA” package. Other packages, referred to as land grid array or “LGA” packages, are secured to the substrate by thin layers or lands formed from solder. This type of package can be very compact. A particular package, commonly referred to as a “chip scale package,” occupies a circuit board area that is equal to or slightly larger than the area of the device incorporated within the package. This reduces the overall size of the assembly and allows the use of short interconnects between various devices on the board, thereby limiting the signal propagation time between devices and increasing the assembly speed. This is advantageous in that the operation becomes easier.

  Assemblies including packages can suffer from stress imposed by differential thermal expansion and contraction of the device and substrate. During operation and manufacture, semiconductor chips tend to expand and contract at a magnitude different from the magnitude of circuit board expansion and contraction. These effects tend to move the terminals relative to the contact pads on the circuit board when the terminals of the package are secured to the chip or other device, for example by using solder. This places stress on the solder connecting the terminals to the contact pads on the circuit board. U.S. Pat. Nos. 5,679,977, 5,148,266, 5,148,265, which are hereby incorporated by reference. As disclosed in certain preferred embodiments of US Pat. Nos. 5,455,390 and 5,518,964, a semiconductor chip package is a chip or other device that is incorporated into the package. Can have terminals that can move relative to Such movement can compensate for a significant degree of differential expansion and contraction.

  Inspection of packaged devices causes other complications. In some manufacturing processes, it is necessary to make a temporary connection between the terminals of the package device and the inspection device and to operate the device with these connections in order for the device to be fully functional. is there. Typically, these temporary connections must be made without coupling the package terminals to the inspection device. It is important to ensure that all of the terminals are connected to the conductive elements of the inspection device. However, it is difficult to make a connection by pressing the package against a simple inspection device such as a normal circuit board with flat contact pads. If the package terminals are not on the same plane, or if the conductive elements of the inspection device are not on the same plane, some of the terminals will not contact their corresponding contact pads on the inspection device. For example, in a BGA package, some solder balls may be located at different heights due to the difference in diameter of solder balls attached to terminals and the non-planarity of the chip carrier.

  These problems can be mitigated by using a specially configured inspection device that has features adapted to compensate for non-planarity. However, such features increase the cost of the inspection device and in some cases introduce some lack of reliability to the inspection device itself. This is particularly undesirable because the inspection device and the engagement between the inspection device and the device must be more reliable than the package device itself in order to perform a meaningful inspection. Also, devices that are adapted to operate at high frequencies generally must be inspected by applying a high frequency signal. This requirement places constraints on the electrical characteristics of the signal path in the inspection device, thereby further complicating the structure of the inspection device.

  Also, when inspecting a package device and wafer in which solder balls are connected to terminals, the solder tends to accumulate on the parts of the inspection apparatus that engage with the solder balls. This accumulation of solder residue can shorten the life of the inspection device and impair its reliability.

  Various solutions have been proposed to address the aforementioned problems. Certain packages disclosed in the aforementioned patents have terminals that are movable relative to the microelectronic device. Such movement can compensate to some extent for the non-planarity of the terminal under inspection.

  Both of these are Nishiguchi. et. Nos. 5,196,726 and 5,214,308 issued to al., in which a bump lead on the surface of a chip is received in a cup-shaped socket on a substrate and a low melting point material Discloses a BGA type approach that is coupled into the socket. Beaman. et. U.S. Pat. No. 4,975,079 issued to al discloses a chip inspection socket in which a dome-shaped contact on an inspection substrate is placed in a conical guide. The chip is pressed against the substrate so that the solder balls enter the conical guide and engage the dome shaped pins on the substrate. Sufficient force is applied so that the dome-shaped pins actually deform the solder balls of the chip.

  A further example of a BGA socket is disclosed in commonly assigned US Pat. No. 5,802,699, issued September 8, 1998, which is incorporated herein by reference. Can be found in the description. The '699 patent discloses a sheet-like connector having a plurality of holes. Each hole is provided with at least one elastic thin-layer contact that extends inward over one hole. The bump lead of the BGA device is pushed into the hole so that the bump lead is engaged with the contact. The assembly can be inspected and the bump leads can be non-removably coupled to the contacts if deemed acceptable.

  US Pat. No. 6,202,297, issued March 20, 2001, which is hereby incorporated by reference in its entirety, has bump leads. A connector for a microelectronic device and a method for manufacturing and using the connector are disclosed. In one embodiment of the '297 patent, the dielectric substrate has a plurality of posts extending upward from the front surface. The posts may be arranged in an array of post groups, where each post group defines a gap between them. A substantially laminar contact extends from the top of each post. In order to inspect the device, each of the device's bump leads is inserted into a corresponding gap, thereby engaging a contact that wipes against the bump lead as it continues to be inserted. Generally, as the bump lead is inserted into the gap, the tip of the contact is deflected downward toward the substrate and away from the center of the gap.

  Co-assigned U.S. Pat. No. 6,177,636, which is hereby incorporated by reference, makes an interconnection between a microelectronic device and a support substrate. Methods and apparatus for disclosing are disclosed. In one preferred embodiment of the '636 patent, a method of forming an interconnect component for a microelectronic device includes providing a flexible chip carrier having first and second surfaces, the first surface of the chip carrier being And bonding a conductive sheet to it. The conductive sheet is then selectively etched to form a plurality of substantially rigid posts. A compliant layer is provided on the second surface of the support structure, and a microelectronic device, such as a semiconductor chip, is engaged with the compliant layer, so that the compliant layer is disposed between the microelectronic device and the chip carrier. The post remains protruding from the exposed surface of the chip carrier. The post is electrically connected to the microelectronic device. The post forms a protruding package terminal that can be engaged in a socket or soldered to a functional part of a substrate, such as a circuit panel. Since the post can move relative to the microelectronic device, such a package substantially adjusts the thermal coefficient of expansion mismatch between the device and the support substrate during device use. Further, the tips of the posts can be on the same plane or substantially the same plane.

Recently, DRAM packages have been developed that operate at frequencies above several GHz, which can make it difficult to utilize wire bonding interconnects due to the high impedance of long wires. For conventional flip chip package, the thermal mismatch between the printed circuit board (CTE14-16) and silicon over emissions (CTE3-4) is may cause BGA delamination around. Accordingly, it is preferred that the underball packaging layer be sufficiently compliant (eg, low modulus and thickness) to compensate for mechanical stresses that occur during thermal cycling.

  Lithographic methods have many drawbacks. The first disadvantage is that the compliant layer has a thickness of about 40 microns formed by a spin coating process that requires a very low rpm. Such compliant layers tend to be non-uniform due to the low rpm. A second problem is that the lithographic process results in a structure with straight walls or opposite angle walls, which results in high stress metallization at the top and bottom bump deflection. The screen printing method is 1) the accuracy of the screen printing process for polymers is low, so the resulting bump thickness variation is 50-60 microns, and 2) due to the large amount of deformed bumps. The screen printing process has many disadvantages including low yield.

  Despite the above developments, there is still a need for improved methods of forming microelectronic packages and microelectronic packages having compliant underball bumps, such as DDR packages having compliant underball bumps. .

The present invention provides an improved method for forming microelectronic packages having compliant underball bumps such as silicon underball bumps (SUB). In one embodiment, the present invention uses a flattening step, during which the screen printed bumps are ground using a conventional grinder. After grinding the bumps, sharp edges on the bump may be smoothed by depositing a photoimageable layer such photoimageable silicone over emissions. Thus, in one embodiment, compliant bumps are screen printed on the wafer, a protective coating is applied over the screen printed compliant bumps, and the screen printed bumps are planarized using a grinding method to further By smoothing the ground compliant bump with the addition of a photoimageable compliant layer, an underball bump is formed at least partially.

In one preferred embodiment of the present invention, a method of forming a microelectronic assembly includes providing a microelectronic device having a first surface and contacts accessible on the first surface. The microelectronic element can include a semiconductor wafer, a wafer having one or more memory chips, or a wafer having one or more double data rate (DDR) chips, such as a DDR3 or DDR4 chip. In one embodiment, the microelectronic device may include a single chip, such as a single memory chip. The method includes providing compliant bumps over a first surface of the microelectronic device and depositing a sacrificial layer over the compliant bumps and over the first surface of the microelectronic device, wherein the sacrificial layer Covers compliant bumps. The sacrificial layer may be a photoimageable layer. The sacrificial layer may comprise a silicone over emissions.

In one embodiment, silicone chromatography emission material (3-2000MPa) is a good candidate for the under ball dielectric or compliant layer. For these materials, there are preferably at least two types of application methods. The first method involves printing a silicone over emissions materials such as WL-6910 sold by Dow Corning. The second method involves using a photoimageable material. These two methods may be used alone or in combination.

  The method desirably includes grinding the sacrificial layer and the compliant bump to planarize the upper surface of the compliant bump so that the planarized upper surface of the compliant bump is accessible through the sacrificial layer. In one embodiment, it is preferred that the planarized top surface is substantially flat. The compliant bump desirably has a sloped side surrounding the planarized top surface so that the sloped side is exposed during the step of removing the sacrificial layer. After the grinding step, the sacrificial layer is removed to expose the portions of the compliant bumps and contacts that surround the planarized top surface. A conductive trace is preferably provided having a first end electrically connected to the contact and a second end located on the planarized top surface of the compliant bump. The conductive traces are preferably formed from conductive materials such as copper, gold, nickel, and alloys, combinations thereof, and composites thereof. Conductive elements such as solder balls, conductive posts, and conductive pins may be provided in contact with the second end of the conductive trace. The conductive element may be formed from a conductive material such as copper, copper alloy, gold, and combinations thereof. The method may also include dicing the microelectronic device to provide individual chip packages having at least one chip.

In one preferred embodiment, after removing the sacrificial layer, silicon chromatography emission layer is deposited over the first surface and the compliant bumps of the microelectronic device. Silicone over down layer may be selectively removed to expose the contacts accessible at the first surface of the microelectronic device.

  In one embodiment, the method includes providing a conductive post in contact with the second end of the conductive trace, the conductive post being located on the compliant bump and from the first surface of the microelectronic device. Projecting away, thereby electrically interconnecting the conductive posts with the contacts of the microelectronic element. The conductive post preferably has a tip that defines the highest point in the microelectronic assembly.

In one embodiment, the compliant bump deposits a layer of material having a modulus in the range of 3-2000 MPa and selectively selects a portion of the layer of low modulus material to form a compliant bump. It is provided by removing. In other embodiments, the compliant bump screen-prints a bump of curable material onto the first surface of the microelectronic element and cures the curable material to form a compliant bump. Provided by. Compliant bumps are silicone over emissions, silicone over emissions polyimide copolymer, softening an epoxy, polyimide, thermoset polymer, a fluoropolymer, and is formed by a material selected from the group consisting of thermoplastic polymers Is desirable.

  In one embodiment, the conductive post has a base adjacent to one of the compliant bumps and a chip away from the compliant bump. The conductive post desirably has a height of about 10 to 500 microns. In another embodiment, the at least one conductive post has a frustoconical shape having a base having a diameter of about 30-600 microns and a tip having a diameter of about 10-200 microns.

In another preferred embodiment of the present invention, a method of forming a microelectronic assembly includes providing a microelectronic element, such as a semiconductor wafer or DDR chip, having a first surface and contacts accessible on the first surface, Providing a dielectric bump over the first surface of the electronic device and depositing a sacrificial layer over the dielectric bump. Dielectric bumps, silicone over emissions, silicone over emissions polyimide copolymer or hybrid polymers, softening an epoxy, polyimide, thermoset polymer, a fluoropolymer, and may be formed from a material such as a thermoplastic polymer. The method may include grinding the sacrificial layer and the dielectric bump to planarize the top surface of the dielectric bump so that the planarized top surface is accessible through the sacrificial layer. After the grinding step, the sacrificial layer may be removed to further expose the dielectric bumps and expose the contacts. A dielectric layer may be deposited over the first surface of the microelectronic device and over the dielectric bumps. The dielectric layer may be selectively removed to expose contacts accessible at the first surface of the microelectronic element. A conductive trace may be formed having a first end electrically connected to the contact and a second end located on the planarized top surface of the dielectric bump. Conductive elements such as solder balls, conductive posts, and conductive pins may be provided in contact with the second end of the conductive trace.

  The conductive traces may be formed from conductive materials such as copper, gold, nickel, and alloys, combinations thereof, and composites thereof. The conductive element may be a conductive post disposed on the dielectric bump, where each conductive post has a height of about 50-300 microns. The conductive element is preferably formed from a conductive material such as copper, copper alloy, gold, and combinations thereof.

In another preferred embodiment of the present invention, a method of forming a microelectronic assembly forms a semiconductor wafer having a first surface and contacts accessible on the first surface, on the first surface of the semiconductor wafer. Compliant bumps over, depositing a sacrificial layer over the compliant bumps, grinding the sacrificial layer and compliant bumps to planarize the top surface of the compliant bumps, thereby providing a planarized top surface of the compliant bumps Enabling access through the sacrificial layer. Method, after grinding step, by removing the sacrificial layer to expose the compliant bumps and the contact, depositing the silicon over down layer over the first surface and the compliant bumps of the microelectronic device, a semiconductor wafer it may include selectively removing the silicon over down layer to expose the contacts accessible at the first surface. A conductive trace is provided having a first end electrically connected to the contact and a second end located on the planarized top surface of the compliant bump. A conductive element is preferably provided in contact with the second end of the conductive trace. The microelectronic element may be diced to provide a plurality of individual chip packages.

  The conductive element may be a conductive post. The conductive element or post may be plated on the second end of the conductive trace such that the conductive element / post is located on the compliant bump.

The microelectronic assembly includes a semiconductor wafer having a first surface and contacts accessible on the first surface, and compliant bumps located on the first surface of the semiconductor wafer, each compliant bump being planar. And a compliant bump having a flat upper surface. Assembly desirably includes a silicon over down layer located on the first surface and the compliant on the bump of the semiconductor wafer, in which case the flat upper surface and the contact of the compliant bumps accessible through silicone over down layer. The assembly includes a conductive trace having a first end electrically connected to the contact and a second end located on the planarized top surface of the compliant bump, and a second end of the conductive trace; Preferably in contact with the conductive element. The conductive element may be a solder ball, a conductive post, or a conductive pin. The semiconductor wafer may include one or more memory chips. The wafer may also include one or more double data rate (DDR) chips, such as DDR3 or DDR4 chips.

In a preferred embodiment, the compliant bump or compliant layer is preferably formed from a material having a low modulus of elasticity. Compliant layer, silicon over emissions, softening an epoxy, polyimide, thermoset polymer, a fluoropolymer, and may be formed from a material such as a thermoplastic polymer.

  The microelectronic assembly desirably includes elongated conductive elements to electrically interconnect conductive elements (eg, conductive posts) and microelectronic device contacts. The elongated conductive element may include materials such as copper, gold, nickel, and alloys, combinations thereof, and composites thereof. In a preferred embodiment, the elongated conductive element may be a bond ribbon or a conductive trace. The elongated conductive element preferably extends over the compliant bump or over the dielectric bump.

  In one embodiment, at least one of the conductive posts may be disposed on at least one of the compliant bumps. In other preferred embodiments, each conductive post is disposed on one of the compliant bumps. In still other preferred embodiments, two or more conductive posts may be disposed on a single compliant bump. Each conductive post desirably has a base adjacent to the compliant bump or compliant layer and a chip away from the compliant bump or compliant layer. The conductive post preferably has a height that is higher than the thickness of the solder mask so that the post is the tallest / tallest structure on the microelectronic assembly. As a result, during testing of the microelectronic assembly, the tips of the conductive posts are the first element for engaging the conductive pads on the test board. In one preferred embodiment, it is desirable that the conductive posts have a height of about 50-300 microns. In one preferred embodiment, at least one of the conductive posts has a frustoconical shape with a base having a diameter of about 100-600 microns and a tip having a diameter of about 40-200 microns. The conductive posts may be formed from a conductive material such as copper, copper alloy, gold, and combinations thereof.

  The compliant bump preferably has an upper surface spaced from the first surface of the microelectronic element and an inclined surface extending between the upper surface of the compliant bump and the first surface of the microelectronic element. The conductive traces preferably extend over the compliant bump ramp.

  These preferred embodiments of the present invention and other preferred embodiments are described in further detail below.

1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 6 illustrates a method of forming a microelectronic assembly according to another preferred embodiment of the present invention. 6 illustrates a method of forming a microelectronic assembly according to another preferred embodiment of the present invention. 6 illustrates a method of forming a microelectronic assembly according to another preferred embodiment of the present invention. Fig. 4 illustrates a method of forming a microelectronic assembly according to a further preferred embodiment of the invention. Fig. 4 illustrates a method of forming a microelectronic assembly according to a further preferred embodiment of the invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 1 illustrates a method of forming a microelectronic assembly according to one preferred embodiment of the present invention. 14D shows the microelectronic assembly of FIG. 14J abutting against an inspection board. FIG.

  Referring to FIG. 1 according to a preferred embodiment of the present invention, the wafer 20 includes a top surface 22, which has contacts (not shown) accessible at the top surface. Wafer 20 also includes a lower surface 24 opposite to upper surface 22. In one embodiment, the wafer is a semiconductor wafer having a plurality of semiconductor chips. In other embodiments, the wafer has a plurality of memory chips, such as DRAM chips or DDR chips. In a highly preferred embodiment, the wafer has one or more DDR3 chips or DDR4 chips.

Referring to FIG. 2, a stencil or screen 26 having an opening 28 is juxtaposed with the upper surface 22 of the wafer 20. Hardenable material 30 such as silicone over down, through the opening 28 of the stencil, is screen printed on the upper surface 22 of the wafer 20. The screen printed material 30 preferably forms a plurality of bumps 32 of curable material located over the first surface 22 of the wafer 20. The plurality of curable bumps 32 preferably do not cover contacts (not shown) that are accessible on the first surface 22 of the wafer 20. After the bumps are stencil printed on the wafer, the bumps 32 are cured to provide compliant bumps.

In one embodiment, the wafer may be replaced with a single microelectronic chip such as a memory chip. A dielectric passivation layer (not shown) may be deposited or deposited on the top surface 22 of the wafer 20. The passivation layer may be a SiO ₂ passivation layer commonly found on the contact support surface of the semiconductor chip. In other embodiments, a separate dielectric passivating layer such as epoxy resin, polyimide resin, photoimageable dielectric may be used. If a separate passivation layer is used, the passivation layer is spun on the top surface and planar using any one of the electronic grade adhesives commonly known and used by those skilled in the art. A typical sheet form or a dielectric sheet may be laminated on top. The passivation layer covers the top surface 22 of the wafer 20 and exposed contacts (not shown) so that conductive elements such as elongated traces or bond ribbons can be attached to the contacts (eg, by plating). It is preferable to leave.

In one embodiment, compliant bumps are preferably deposited or laminated on the exposed surface of the passive layer (not shown). Compliant Bump is commonly assigned U.S. Patent Nos. 6,211,572, 6,284,563, which are incorporated herein by reference. 6,465,878, 6,847,101, and 6,847,107, and co-pending US applications 09 / 020,647 and 10 / 873,883 may be formed and / or have a shape as disclosed therein [TESSERA 078 caseline]. Compliant bumps may be stencil printed, screen printed, or transfer molded onto the passive layer using a curable liquid that is applied to the passive layer when cured. Alternatively, the compliant bumps may be attached to the exposed surface of the passive layer in the form of a cured compliant pad using an electronic grade adhesive. The compliant bumps may be formed from a wide variety of materials, such as low modulus elastic materials. Compliant bumps are silicone over emissions, softening an epoxy, and polyimide, other thermoset polymer, a fluoropolymer, and may be made from polymeric materials and other materials, such as a thermoplastic polymer .

  A plating seed layer (not shown) may be deposited on the assembly described above, for example by using a sputtering process. Typical plating seed layer materials include palladium (in electroless plating), titanium, tungsten nickel, and chromium. However, in other preferred embodiments, a seed layer formed primarily from copper may be used.

  The conductive trace electrically interconnects the contacts near the first end of the conductive trace and extends to a second end located on one of the compliant bumps. Is preferred. The conductive traces may be plated directly on the contacts. Preferred conductive trace materials include copper, gold, nickel, and alloys, combinations thereof, and composites thereof.

  A solder mask layer may be deposited or laminated over the top of the assembly so that only the second end of the conductive trace is exposed. The mask layer may be a dielectric material. The solder mask may comprise a screen printed, exposed and developed or laminated sheet, a photoresist material, or may be deposited or laminated on the assembly, a paraline epoxy resin, a polyimide resin, A fluoropolymer or the like may be provided.

  Referring to FIG. 3, a sacrificial protective coating 34 is preferably provided on the compliant bump 32. The sacrificial protective coating 34 covers the compliant bumps, the first surface 22 of the wafer 20, and contacts (not shown) accessible on the first surface of the wafer. As will be described in more detail below, the sacrificial protective layer 34 provides a support matrix for the compliant bumps 32 and protects the first surface 22 of the wafer 20 during further processing steps.

  Referring to FIG. 4, the sacrificial protective layer 34 and the compliant bump 32 are preferably planarized so as to form a flat plane on the bump. In one embodiment, the compliant bump is ground or polished to remove a portion of the compliant bump and sacrificial protective layer. As shown in FIG. 4, a part of the sacrificial protective layer 34 is removed so as to expose a part of the compliant bump 32 (that is, a flat upper surface). The compliant bump is ground or polished to form a substantially flat plane 36 on the compliant bump 32. The flat surface 36 is accessible and / or exposed through the sacrificial protective layer 34. The sacrificial protective layer 34 provides a support matrix that prevents the compliant bumps 32 from moving during the grinding process. The sacrificial layer 34 also protects one or more contacts 38 that are accessible on the first surface 22 of the wafer 20. Thus, the sacrificial protective layer 34 protects the first surface of the wafer and prevents contamination of the first surface that may be caused by residues from the ground compliant bumps 32.

  Referring to FIG. 5, after grinding the compliant bump, the sacrificial layer is removed and the first surface 22 of the wafer 20, one or more contacts 38 accessible on the first surface 22, and the compliant bump 32. The side of is exposed.

Referring to FIG. 6, on the first surface 22 of the wafer, on the grounded compliant bumps 32, and on one or more contacts (not shown), it is also commonly referred to as a rampant layer. A photoimageable layer 40 is deposited. In a preferred embodiment, the photoimageable layer 40 is spin coated on the wafer and compliant bumps. In one preferred embodiment, the layer 40 is a photoimageable silicone over down layer, such as silicone over emissions generally sold under the identifier Dow Corning WL-5150 or WL-6910. The photoimageable layer 40 preferably smoothes any sharp edges found on the ground compliant bump 32. Preferably, sharp edges are removed to avoid stress concentrations so that any conductive elements extending over the edges are not damaged by excessive stress during thermal cycling.

  Referring to FIG. 7, a portion of the photoimageable layer 40 is selectively removed to expose one or more contacts (not shown) that are accessible on the top surface of the wafer 20.

  Referring to FIG. 8, conductive traces 42 are formed on the first surface of wafer 20 and on compliant bumps 32. Conductive traces 42 are provided on a compliant bump 32 and a first end that is electrically interconnected with one or more contacts (not shown) found on the first surface of the wafer. Preferably having a second end located on the surface. The conductive traces may be formed by a method such as depositing the metal and then removing the metal to form an elongated conductive element. After the conductive trace 42 is formed, a solder mask layer 44 may be deposited on the conductive trace 42, the compliant bump 32, and the first surface of the wafer 20. A portion of the solder mask layer 44 may be removed to expose the second end of the conductive trace 42 located over the upper end plane 36 of the compliant bump 32. Conductive elements 46 such as solder balls may be deposited in the openings of the solder mask layer 44 to form electrical interconnections with external elements such as printed circuit boards. A conductive element 46 such as a solder ball is preferably electrically connected to the second end of the conductive trace 42. The conductive element 46 may be reflowed to form a conductive bump that rests on the compliant bump 36. Conductive element 46 preferably contacts one or more contacts on wafer 20 via conductive trace 42.

  Referring to FIG. 8, a conductive element 46 is formed on each second end of the conductive trace. The conductive elements 46 may be plated or deposited such that they protrude above the top surface of the semiconductor wafer or chip. In one preferred embodiment, each conductive element is preferably connected to the second end of the conductive trace.

  In one embodiment, the conductive element 46 may be used to non-removably connect an external substrate such as a printed circuit board and the microelectronic assembly. The conductive element may include a soluble material such as solder. Conductive element 46 may be reflowed to permanently connect the microelectronic assembly and circuit board.

  Referring to FIG. 9, according to another embodiment of the present invention, a microelectronic assembly is formed using one or more of the steps described above with respect to FIGS. The microelectronic assembly includes a photoimageable layer 140 deposited on a ground compliant bump 132 having a planarized top surface.

  Referring to FIG. 10, a portion of the photoimageable layer 140 is selectively removed to expose the flat surface 136 on the compliant bump 132. Removal of the photoimageable layer 140 also exposes one or more contacts 138 that are accessible on the first surface of the wafer 120. Photoimageable layer 140 appears on each bump in the area of compliant bump 132.

  Referring to FIG. 11, a conductive trace 142 is preferably formed on the photoimageable layer 140. The conductive trace 142 preferably extends from the top plane 136 of the compliant bump 132 to one or more contacts (not shown) that are accessible on the first surface of the wafer 120. Conductive trace 142 may be formed by depositing a layer of conductive metal on the wafer and selectively removing the metal to form a conductive trace. A layer of solder resist material 144 is preferably deposited on the conductive trace 142. The solder resist layer 144 may be selectively removed to expose the second end of the conductive trace on the flat surface of the compliant bump 132. A conductive element 146, such as a solder ball, conductive post, or conductive pin, may be deposited on the exposed second end of the conductive trace 142.

  FIG. 12 shows a microelectronic assembly similar to the assembly shown in FIG. The microelectronic assembly includes a semiconductor wafer 220 having a first surface, and one or more contacts 238 are accessible at the first surface. The microelectronic assembly also includes a compliant bump 232 having a flat surface 236.

  Referring to FIG. 13, conductive traces 242 are formed on compliant bumps 232 having a flat surface. The conductive traces have a first end that is electrically interconnected with one or more contacts accessible on the first surface of the wafer 220 and a second end located over the flat surface 236 of the compliant bump 232. Part. A solder mask layer 244 may be deposited on the conductive traces 242. The solder mask layer 244 may be selectively removed to expose the second end of the conductive trace 242 on the flat surface of the compliant bump 232. An elongated conductive post 236 or pin may be provided on the flat surface of the compliant bump 232. In one preferred embodiment, conductive posts 246 are plated on compliant bumps 232. In another preferred embodiment, conductive posts 246 are deposited on compliant bumps using a mold. In still other preferred embodiments, the conductive posts 246 are attached to a flat surface on the compliant bump 232 after being preformed away from the microelectronic assembly. Conductive posts 246 are preferably electrically interconnected with one or more contacts on the wafer via conductive traces 244. In one preferred embodiment, the conductive post 246 has a substantially flat tip. The substantially flat tip 250 of the conductive post 246 may be located in a common plane.

  Post dimensions may vary over a fairly large range. In a preferred embodiment, the post has a height above the upper surface of the compliant layer of about 50-300 microns. Each post 246 has a base adjacent to the compliant bump and a chip 250 spaced from the compliant layer. The conductive posts 246 may be formed from any conductive material, but are preferably formed from metallic materials such as copper, copper alloys, gold, and combinations thereof. For example, the conductive post 246 may be formed from copper, in which case a gold layer is provided on the surface of the post.

  Referring to FIG. 14A, in one preferred embodiment, a semiconductor wafer 320, such as a DRAM wafer, has an upper surface 322 and a lower surface 324 spaced from the upper surface. Wafer 320 includes contacts 338 that are accessible on the top surface thereof. Preferably, compliant bumps 332 are provided on the upper surface 322 of the wafer 320. In one embodiment, compliant bumps 332 are formed by stencil printing or screen printing a chunk of curable material on wafer 320. After the curable material mass has been cured, it is preferably polished or ground to provide compliant bumps 332 having a generally flat top plane 336.

  Referring to FIG. 14B, a seed layer 340 is desirably deposited over the top surface of the wafer 320, over one or more contacts 338, and over compliant bumps 332. In one preferred embodiment, a seed layer is sputtered over the top surface of the wafer. The seed layer 340 may include a conductive metal such as titanium.

  Referring to FIG. 14C, a photoresist layer 345 is deposited on the seed layer 340. In one preferred embodiment, the photoresist layer 345 is an electrophoretic photoresist layer. Thereafter, the photoresist layer is exposed and a portion of the photoresist layer 345 is selectively removed, thereby providing one or more openings 352.

  Referring to FIG. 14D, conductive leads or traces 342 are preferably plated over the openings in the photoresist layer 345. As shown in FIG. 14D, the conductive trace 342 has a first end 354 that contacts a contact 338 on the wafer, and a second end 356 located on the flat surface of the compliant pad 332.

  Referring to FIG. 14E, the photoresist layer 345 is then stripped or removed. Referring to FIG. 14F, a second photoresist layer 358 is deposited over the conductive traces 342, the contacts 338, and the compliant bumps 332. The second photoresist layer 358 may include an electrophoretic photoresist layer. The second resist layer 358 is exposed to form an opening 360 that is aligned with the second end 356 of the conductive trace 342.

  Referring to FIG. 14G, conductive pins 350 are preferably formed on the compliant bumps by electroplating the pins into the openings in the second photoresist layer 358. In one embodiment, the conductive pins are formed from copper.

  Conductive post 350 is preferably electrically interconnected with contacts 338 on the wafer via conductive traces 342.

  Referring to FIG. 14H, after the conductive posts 350 are plated, the second photoresist layer is removed to expose the conductive traces 342. Referring to FIGS. 14H and 14I, the seed layer 340 is removed from the upper surface 322 of the wafer 320.

  Referring to FIG. 14J, a dielectric overcoat layer 362 or solder mask layer is deposited over the top surface of the wafer 320. The dielectric overcoat layer 362 covers a portion of the conductive traces 342 and compliant bumps 332. An opening 364 is formed in the dielectric overcoat layer 362, and the conductive post 350 protrudes through the opening 364.

  Referring to FIG. 15, the wafer level assembly of FIG. 14J may be inspected by providing an inspection board 370 having conductive elements such as probe pins 372. The probe pin 372 is abutted against a conductive post 350 on the microelectronic assembly to burn in and / or inspect the microelectronic assembly. Any non-planarity between the probe pin 372 and the conductive post 350 is compensated by the compliance of the compliant bump 332.

  Conventional die level burn-in (BI) technology utilizes a temporary die carrier for individual die burn-in and inspection. The need to mount individual dies on such a temporary carrier greatly increases the cost of burn-in in mass production technology. Conventional wafer level burn-in (WLBI) techniques generally include a sacrificial metal layer method and a direct contact method. The sacrificial metal layer method requires a temporary redistribution metal layer deposition that is removed after inspection, thus increasing the complexity of the manufacturing process. Other problems are burn-in prior to packaging, and the exposed die is significantly more environmentally affected than packaged products, thus reducing yield due to handling and environmental issues. It is. The direct contact wafer level burn-in method allows simultaneous inspection of many devices. Full wafer contactors that connect to all pins independently of the burn-in system are implemented by microsprings or pogo pins. However, full contact probe cards with very high pin counts and small pitches are very expensive.

  The present invention incorporates compliance within the package. Compliant bumps provided under each individual input / output allow wafer level inspection to be performed without an interposer. This is because compliant bumps compensate for input / output non-planarity due to their deformation during wafer level probing. Also, in the preferred embodiment, copper pins or conductive posts replace BGA spheres to reduce the required probing force and contact resistance. Furthermore, the present invention allows for wafer level burn-in (WLBI) and inspection without facing each of the aforementioned problems.

  Post dimensions may vary over a fairly large range. In one preferred embodiment, the post has a height above the top surface of the compliant layer of about 50-300 microns. Each post 246 has a base adjacent to the compliant bump and a chip 250 spaced from the compliant layer. The conductive posts 246 may be formed from any conductive material, but are preferably formed from metallic materials such as copper, copper alloys, gold, and combinations thereof. For example, the conductive post 246 may be formed from copper, in which case a gold layer is provided on the surface of the post.

  In one preferred embodiment, conventional processes such as plating may form conductive traces, and conductive posts are incorporated by reference in the same application which is hereby incorporated by reference. It may be formed using the method disclosed in human US Pat. No. 6,177,636. In still other preferred embodiments, the conductive posts are manufactured as individual elements and assembled into a microelectronic assembly in any suitable manner that connects the conductive posts to the second end of the conductive traces. May be. In yet another preferred embodiment, the assembly deposits a seed layer and has a conductive trace having a first end connected to the contact of the microelectronic element and a second end disposed on the compliant layer. May be formed by plating the conductive posts on the compliant layer in contact with the conductive traces and removing the seed layer. The assembly may also be formed by electroless plating the conductive posts. The conductive posts may be formed by electroless plating the posts using copper or nickel. In other embodiments, a conductive element, such as a conductive pin or sphere, may be provided over the second end of the conductive trace using any of the methods described herein.

  To inspect the microelectronic assembly, the chip 250 of the conductive post 246 is juxtaposed with the conductive pads of the circuit board. The chip 250 may be pressed against the conductive pad. Compliant bumps 232 allow the tips of the conductive posts to move relative to the contacts on the wafer 220, thereby adjusting for non-planarity and thermal mismatch between the posts and the conductive pads. If inspection of the microelectronic assembly is successful, the assembly may be non-removably attached to a substrate, such as a printed circuit board, by using solder or other soluble or conductive material.

  In one preferred embodiment of the present invention, the conductive posts may be substantially frustoconical, so that the base and tip of each post are substantially circular. In these particular preferred embodiments, the diameter of the base of the post is generally about 100-600 microns, while the diameter of the tip is generally about 40-200 microns. The outer surface of the conductive post may optionally be plated with a highly conductive layer such as gold, gold / nickel, gold / osmium, or gold / palladium, or the post may be soldered to the substrate. Alternatively, it may be plated with a wear-resistant conductive coating such as osmium to ensure a good connection when socketed.

  In a preferred embodiment of the present invention, the post has a shape that facilitates a tilting action that causes the tip to wipe across the contact pad when the tip of each post is engaged with the opposing contact pad. Also good. This tilting action promotes reliable electrical contact. United States by co-pending same applicant filed November 10, 2004 entitled "MICRO PIN GRID ARRAY WITH WIPING ACTION", which is hereby incorporated by reference. As described in more detail in patent application Ser. No. 10 / 985,126, the post is provided with a function that facilitates such wiping action or otherwise facilitates engagement of the post and contacts. Also good. Conductive posts having other shapes and structures that facilitate wiping and / or good electrical contact are incorporated herein by reference to “MICRO PIN GRID WITH PIN MOTION ISOLATION”. US patent application Ser. No. 10 / 985,119 filed Nov. 10, 2004, entitled “MICROELECTRONIC PACKAGES AND METHODS THEREFOR”, filed Dec. 16, 2004 Further details are disclosed in commonly assigned US patent application Ser. No. 11 / 014,439 filed on the same day.

  In one preferred embodiment of the present invention, the present disclosure is incorporated herein by reference for its disclosure to facilitate the formation of electrical interconnections between microelectronic elements and to facilitate inspection of microelectronic packages. The particle coating material as disclosed in US Pat. Nos. 4,804,132 and 5,083,697, which are part of US Pat. It may be provided above. The particle coating material is preferably provided on a conductive component such as a conductive terminal or a chip end of the conductive post. In one particularly preferred embodiment, the particle coating material is a metallized diamond crystal coating material that is selectively electroplated onto the conductive components of the microelectronic device using standard photoresist techniques. In operation, a conductive component with a diamond crystal coating may be pressed onto the opposing contact pad to drill an oxide layer present on the outer surface of the contact pad. The diamond crystal coating facilitates the formation of a reliable electrical interconnect through the oxide layer in addition to the conventional wiping operation.

  Also, the Post is co-pending filed October 6, 2004 entitled “Formation of Circuit With Modification of Feature Height”, which is incorporated herein by reference. Of the same Applicant's US patent application Ser. No. 10 / 959,465.

  Although the present invention is not limited by any particular theory of operation, providing a conductive element on a compliant material as disclosed herein can adjust the thermal mismatch and provide an appropriate electrical interconnect. It is believed to provide a compliant wafer level or chip package that ensures the formation of connections. Also, by using conductive pins or posts, microelectronic assemblies and / or wafers can be inspected by bringing the tips of the conductive posts directly into contact with the contacts on the inspection board without requiring the use of an inspection socket. be able to.

  Although the present disclosure provides a specific sequence for forming the microelectronic assemblies and wafers described herein, the sequence order may be varied and still fall within the scope of the invention.

  In one preferred embodiment, the structure disclosed herein is used to form a test board having compliant layers and conductive elements, solder balls protruding from the compliant layer, conductive posts or conductive pins. May be. The contacts on the bare wafer or die may be brought into contact with the tips of the conductive posts to inspect the wafer or die.

  Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. Accordingly, it will be understood that numerous modifications can be made to the illustrated embodiments and other configurations can be envisioned without departing from the spirit and scope of the invention as defined by the appended claims. I want to be.

Claims (40)

A method of forming a microelectronic assembly comprising:
Providing a microelectronic element having a first surface and a contact accessible on the first surface;
Providing compliant dielectric bumps over the first surface of the microelectronic element;
Depositing a sacrificial layer over the compliant dielectric bump and over the first surface of the microelectronic device, such that the sacrificial layer covers the compliant dielectric bump;
A step of grinding the sacrificial layer and the compliant dielectric bumps, to flatten the upper surface of the compliant dielectric bumps, to expose the planarized upper surface of the compliant dielectric bumps,
Removing at least a portion of the sacrificial layer after the grinding step to expose at least some of the contacts ;
Forming a conductive trace having a first end electrically connected to the contact and a second end located on a planarized top surface of the compliant dielectric bump. How to form.   The method of claim 1, further comprising providing a conductive element that contacts a second end of the conductive trace.   The method of claim 2, wherein the conductive element is selected from the group consisting of a solder ball, a conductive post, and a conductive pin.   The method of claim 1, wherein the contact on the wafer is exposed during the step of removing the sacrificial layer. The method of claim 1, wherein the compliant dielectric bump has a sloping side surface surrounding a planarized top surface, and the sloping side surface is exposed during the step of removing the sacrificial layer. After the step of removing the sacrificial layer, depositing a silicon over down layer over the first surface and the compliant dielectric bumps of the microelectronic device,
The method of claim 1 the further comprising 1 of the step of the silicon over down layer to expose the contacts selectively removing the surface of the microelectronic device.   The method of claim 1, wherein the microelectronic device comprises a semiconductor wafer.   The method of claim 1, wherein the microelectronic device comprises at least one memory chip.   The method of claim 1, wherein the microelectronic device comprises at least one DDR chip.   The method of claim 7, further comprising dicing the semiconductor wafer. The method further includes providing a conductive post that contacts a second end of the conductive trace, the conductive post being located on the compliant dielectric bump and projecting away from the first surface of the microelectronic device. The method of claim 1, wherein the conductive post is electrically interconnected with the contact of the microelectronic element.   The method of claim 11, wherein the conductive post has a tip that defines a highest point in the microelectronic assembly. Providing the compliant dielectric bump comprises:
Deposit a layer of material with low elastic modulus,
Selectively removing a portion of the layer of low modulus material to form the compliant dielectric bump;
The method of claim 1, comprising: Providing the compliant dielectric bump comprises:
Bump printing of a curable material on the first surface of the microelectronic element;
Curing the curable material to form the compliant dielectric bump;
The method of claim 1, comprising:   The method of claim 1, wherein the sacrificial layer comprises a photoimageable layer. The method of claim 15 wherein the sacrificial layer is one that includes a silicone over emissions. The compliant dielectric bumps, the silicon over emissions, and softened epoxy, wherein the polyimide, a thermosetting polymer, those comprising a fluoropolymer, a material selected from the group consisting of a thermoplastic polymer Item 2. The method according to Item 1. The method of claim 1, wherein after the grinding step, the compliant dielectric bump has a substantially flat top surface.   The method of claim 1, wherein the conductive trace comprises a material selected from the group consisting of copper, gold, nickel, alloys, combinations thereof, and composites thereof. Each of the conductive posts, base and method of claim 1 are those having a tip spaced from one of said compliant dielectric bump adjacent to one of the compliant dielectric bumps . 20. The method of claim 19, wherein each of the conductive posts has a height in the range of 50 to 300 microns.   20. The method of claim 19, wherein at least one of the conductive posts has a frustoconical shape having a base having a diameter of 100 to 600 microns and a tip having a diameter of 40 to 200 microns.   The method of claim 1, wherein the conductive element comprises a material selected from the group consisting of copper, copper alloys, gold, and combinations thereof. A method of forming a microelectronic assembly comprising:
Providing a microelectronic element having a first surface and a contact accessible on the first surface;
Providing a dielectric bump over the first surface of the microelectronic element;
Depositing a sacrificial layer over the dielectric bump;
Grinding the sacrificial layer and the dielectric bump to planarize the top surface of the dielectric bump and exposing the planarized top surface;
Removing at least a portion of the sacrificial layer after the grinding step to expose the dielectric bump and the contact;
Depositing a dielectric layer over the first surface of the microelectronic device and over the dielectric bump;
Selectively removing said dielectric layer to expose the contacts on the first surface of the microelectronic device,
Forming a conductive trace having a first end electrically connected to the contact and a second end located on a planarized top surface of the dielectric bump;
Providing a conductive element in contact with the second end of the conductive trace.   25. The method of claim 24, wherein the conductive element is selected from the group consisting of a solder ball, a conductive post, and a conductive pin.   26. The method of claim 25, wherein the microelectronic device comprises a semiconductor wafer that includes one or more memory chips. The method of claim 24 wherein the sacrificial layer is a photoimageable of those comprising a silicone over emissions. The dielectric bump The method of claim 24 in which comprises a material selected from the group consisting of silicon over emissions softened epoxy and polyimide and a thermosetting polymer and a fluoropolymer and a thermoplastic polymer.   25. The method of claim 24, wherein after the grinding step, the dielectric bump has a substantially flat top surface.   25. The method of claim 24, wherein the conductive trace comprises a material selected from the group consisting of copper, gold, nickel and alloys, combinations thereof, and composites thereof. The method of claim 24, wherein the conductive elements comprise conductive posts disposed on the dielectric bumps, each of the conductive posts having a height in the range of 50 to 300 microns.   25. The method of claim 24, wherein the conductive element comprises a material selected from the group consisting of copper, copper alloys, gold, and combinations thereof. A method of forming a microelectronic assembly comprising:
Providing a semiconductor wafer having a first surface and contacts accessible on the first surface;
Forming compliant dielectric bumps over a first surface of the semiconductor wafer;
Depositing a sacrificial layer over the compliant dielectric bump;
A step of grinding the sacrificial layer and the compliant dielectric bumps, to flatten the upper surface of the compliant dielectric bumps, to expose the planarized upper surface of the compliant dielectric bumps,
Removing the sacrificial layer after the grinding step to expose the compliant dielectric bump and the contact;
Depositing a silicon over down layer over the first surface and the compliant dielectric bumps of the microelectronic device,
Selectively removing said silicon over down layer to expose the contacts accessible at the first surface of the semiconductor wafer,
Forming a conductive trace having a first end electrically connected to the contact and a second end located on a planarized top surface of the compliant dielectric bump;
Providing a conductive element in contact with the second end of the conductive trace.   34. The method of claim 33, wherein the conductive element comprises a conductive post. 35. The method of claim 34, further comprising plating the conductive post overlying the compliant dielectric bump on a second end of the conductive trace.   34. The method of claim 33, further comprising the step of dicing the semiconductor wafer to provide a plurality of individual chip packages. A semiconductor wafer having a first surface and contacts accessible on the first surface;
A compliant dielectric bump located on a first surface of said semiconductor wafer, each of the compliant dielectric bump has a flat upper surface, and the compliant dielectric bumps,
A dielectric layer located on at least an end of the first surface of the semiconductor wafer and on the compliant dielectric bump, wherein a flat top surface of the compliant dielectric bump and the contact are accessible through the dielectric layer; A dielectric layer;
A conductive trace formed on the dielectric layer and electrically connected to the contact, the conductive trace extending from a planarized upper surface of the compliant dielectric bump to the contact ;
A microelectronic assembly comprising: a conductive element covering the planarized top surface and in contact with the conductive trace.   38. The assembly of claim 37, wherein the conductive element is selected from the group consisting of solder balls, conductive posts, and conductive pins.   38. The assembly of claim 37, wherein the semiconductor wafer comprises one or more memory chips.   40. The assembly of claim 39, wherein the wafer comprises one or more double data rate (DDR) chips.

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