JPS57115850A - Chip carrier for semiconductor ic - Google Patents

Chip carrier for semiconductor ic

Info

Publication number
JPS57115850A
JPS57115850A JP194481A JP194481A JPS57115850A JP S57115850 A JPS57115850 A JP S57115850A JP 194481 A JP194481 A JP 194481A JP 194481 A JP194481 A JP 194481A JP S57115850 A JPS57115850 A JP S57115850A
Authority
JP
Japan
Prior art keywords
substrate
frame
pads
leading out
out terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP194481A
Other languages
Japanese (ja)
Inventor
Yoshimasa Hiki
Takashi Nakahara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP194481A priority Critical patent/JPS57115850A/en
Publication of JPS57115850A publication Critical patent/JPS57115850A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To obtain a chip carrier provided with more leading out terminals than a traditional one in spite of its size similar to the traditional one by a method wherein the inner as well as the outer periphery of a frame equivalent to a substrate it is mounted upon in point of horizontal dimensions is provided with terminal pads. CONSTITUTION:A metal layer 12 for mounting an IC chip is provided at the central part on a surface of an exemplifiedly ceramic material made insulator substrate 11. Formed spreading around the outer periphery of the metal layer 12 on the substrate 11 are a first group of pads 13 for leading out terminals for connection with the IC chip, a bonding pad 14, a connecting pad 15, metal wirings 16 and 17. A frame 21 with its horizontal dimensions same as the substrate 11 is mounted on the substrate 11 to make a chip carrier. The frame 21 is usually provided only with a plurality of second pads 22 for leading out terminals but a third group of pads 23 for leading out terminals may be addedly provided on the inner periphery of the frame 21 without increasing horizontal dimensions.
JP194481A 1981-01-10 1981-01-10 Chip carrier for semiconductor ic Pending JPS57115850A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP194481A JPS57115850A (en) 1981-01-10 1981-01-10 Chip carrier for semiconductor ic

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP194481A JPS57115850A (en) 1981-01-10 1981-01-10 Chip carrier for semiconductor ic

Publications (1)

Publication Number Publication Date
JPS57115850A true JPS57115850A (en) 1982-07-19

Family

ID=11515719

Family Applications (1)

Application Number Title Priority Date Filing Date
JP194481A Pending JPS57115850A (en) 1981-01-10 1981-01-10 Chip carrier for semiconductor ic

Country Status (1)

Country Link
JP (1) JPS57115850A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2538961A1 (en) * 1982-12-30 1984-07-06 Europ Composants Electron EMBASE FOR INTEGRATED CIRCUIT
JPS59501564A (en) * 1982-08-10 1984-08-30 ダウテイ・エレクトロニク・コンポーネンツ・リミテツド electric circuit unit
EP0790653A3 (en) * 1995-09-01 1998-04-15 Canon Kabushiki Kaisha IC package and its assembly method
EP0932328A4 (en) * 1995-12-22 1999-10-27 Ibiden Co Ltd Substrate for mounting electronic part and process for manufacturing the same
EP1050906A1 (en) * 1999-05-06 2000-11-08 Murata Manufacturing Co., Ltd. Package for electronic components
JP2010238821A (en) * 2009-03-30 2010-10-21 Sony Corp Multilayer wiring substrate, stack structure sensor package, and method of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59501564A (en) * 1982-08-10 1984-08-30 ダウテイ・エレクトロニク・コンポーネンツ・リミテツド electric circuit unit
FR2538961A1 (en) * 1982-12-30 1984-07-06 Europ Composants Electron EMBASE FOR INTEGRATED CIRCUIT
US4568796A (en) * 1982-12-30 1986-02-04 Lcc.Cice-Compagnie Europenne De Composants Electroniques Housing carrier for integrated circuit
EP0790653A3 (en) * 1995-09-01 1998-04-15 Canon Kabushiki Kaisha IC package and its assembly method
US6383835B1 (en) 1995-09-01 2002-05-07 Canon Kabushiki Kaisha IC package having a conductive material at least partially filling a recess
EP0932328A4 (en) * 1995-12-22 1999-10-27 Ibiden Co Ltd Substrate for mounting electronic part and process for manufacturing the same
US6201185B1 (en) 1995-12-22 2001-03-13 Ibiden Co., Ltd. Substrate for mounting electronic part having conductive projections and process for manufacturing the same
EP1050906A1 (en) * 1999-05-06 2000-11-08 Murata Manufacturing Co., Ltd. Package for electronic components
KR100372042B1 (en) * 1999-05-06 2003-02-14 가부시키가이샤 무라타 세이사쿠쇼 Package for electronic components
JP2010238821A (en) * 2009-03-30 2010-10-21 Sony Corp Multilayer wiring substrate, stack structure sensor package, and method of manufacturing the same
US8446002B2 (en) 2009-03-30 2013-05-21 Sony Corporation Multilayer wiring substrate having a castellation structure

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