JPS6476748A - Semiconductor circuit device - Google Patents

Semiconductor circuit device

Info

Publication number
JPS6476748A
JPS6476748A JP62234318A JP23431887A JPS6476748A JP S6476748 A JPS6476748 A JP S6476748A JP 62234318 A JP62234318 A JP 62234318A JP 23431887 A JP23431887 A JP 23431887A JP S6476748 A JPS6476748 A JP S6476748A
Authority
JP
Japan
Prior art keywords
package element
wiring board
printed wiring
usual
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62234318A
Other languages
Japanese (ja)
Inventor
Hideto Nitta
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62234318A priority Critical patent/JPS6476748A/en
Publication of JPS6476748A publication Critical patent/JPS6476748A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components

Abstract

PURPOSE:To decrease the wiring density of a printed wiring board, and reduce the cost of printed wiring board, by alternately arranging and connecting a usual IC package element and the other IC package element in which functional arrangement of external leads is inverted. CONSTITUTION:An IC package element 10 and a usual IC package element 10' are alternately arranged on a printed wiring board. As to external terminals 1-8 of each 10 package element, the same number terminals are connected with each other by wiring, in the manner in which the number of cross parts 9 becomes minimum on the printed wiring board. For example, in the case of wireconnecting an external terminal 8 of the usual IC package element 10 and an external terminal 8 of the IC package element 10, the wiring on the printed wiring board is enabled without crossing the other wiring. Further, in the case of mutually connecting external leads 1 of each IC package, three cross parts 9 are sufficient for the case where six cross parts are required in total by two usual blocks.
JP62234318A 1987-09-17 1987-09-17 Semiconductor circuit device Pending JPS6476748A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62234318A JPS6476748A (en) 1987-09-17 1987-09-17 Semiconductor circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62234318A JPS6476748A (en) 1987-09-17 1987-09-17 Semiconductor circuit device

Publications (1)

Publication Number Publication Date
JPS6476748A true JPS6476748A (en) 1989-03-22

Family

ID=16969130

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62234318A Pending JPS6476748A (en) 1987-09-17 1987-09-17 Semiconductor circuit device

Country Status (1)

Country Link
JP (1) JPS6476748A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
US7289332B2 (en) * 2004-06-16 2007-10-30 Liberty University Mirror image electrical packages and system for using same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
US5420756A (en) * 1992-06-19 1995-05-30 Kabushiki Kaisha Toshiba Memory card including stacked semiconductor memory elements located on a printed circuit board having a straight wiring pattern
US7289332B2 (en) * 2004-06-16 2007-10-30 Liberty University Mirror image electrical packages and system for using same

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