GB1513893A - Integrated circuit structure - Google Patents
Integrated circuit structureInfo
- Publication number
- GB1513893A GB1513893A GB2187575A GB2187575A GB1513893A GB 1513893 A GB1513893 A GB 1513893A GB 2187575 A GB2187575 A GB 2187575A GB 2187575 A GB2187575 A GB 2187575A GB 1513893 A GB1513893 A GB 1513893A
- Authority
- GB
- United Kingdom
- Prior art keywords
- cells
- level
- adjacent rows
- metallization
- groups
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001465 metallisation Methods 0.000 abstract 3
- 238000009413 insulation Methods 0.000 abstract 2
- 239000004020 conductor Substances 0.000 abstract 1
- 239000011810 insulating material Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
1513893 Integrated circuits INTERNATIONAL BUSINESS MACHINES CORP 21 May 1975 [26 June 1974] 21875/75 Heading H1K The component logic circuits of a planar LSI chip are arranged in a rectangular array with a level of metallization, disposed above the array on a layer of insulating material, comprising (a) a plurality of mutally parallel conductive lines arranged in groups, each group being disposed above and extending parallel to a respective interface between adjacent rows of cell, and being selectively connected to some of the cells to provide interconnections between and voltage level supplies to the cells, and (b) clustered conductive patterns disposed above the cells between the groups to provide the internal connections of the cells. In a described arrangement in which each cell comprises a Schottky diode clamped TTL circuit, the cells are arranged in 4 x 2 blocks with spaces between adjacent rows and columns of blocks, each cell being a mirror image of the corresponding cells in the adjacent rows and columns. The groups of parallel lines are located over the spaces between adjacent rows. A second level of metallization is present on insulation overlying the first level, consisting of conductive lines normal to those of the first level providing further interconnections between the cells and cross-over connections between non-adjacent lines of the first level, while a third level constitutes a voltage distribution bus arrangement supplying the voltage level conductors in the lower levels. Generally conventional processing steps for production of the components of the LSI and the various levels of metallization and intervening insulation are described in detail.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48346374A | 1974-06-26 | 1974-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1513893A true GB1513893A (en) | 1978-06-14 |
Family
ID=23920133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB2187575A Expired GB1513893A (en) | 1974-06-26 | 1975-05-21 | Integrated circuit structure |
Country Status (8)
Country | Link |
---|---|
JP (2) | JPS5125085A (en) |
CA (1) | CA1024661A (en) |
CH (1) | CH583970A5 (en) |
DE (1) | DE2523221A1 (en) |
ES (1) | ES438666A1 (en) |
FR (1) | FR2276693A1 (en) |
GB (1) | GB1513893A (en) |
IT (1) | IT1038108B (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7317251B2 (en) | 2003-04-11 | 2008-01-08 | Infineon Technologies, Ag | Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components |
Families Citing this family (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2823555A1 (en) * | 1977-05-31 | 1978-12-07 | Fujitsu Ltd | CELL-SHAPED INTEGRATED CIRCUIT |
CA1102009A (en) * | 1977-09-06 | 1981-05-26 | Algirdas J. Gruodis | Integrated circuit layout utilizing separated active circuit and wiring regions |
DE2822011C3 (en) * | 1978-05-19 | 1987-09-10 | Fujitsu Ltd., Kawasaki, Kanagawa | Semiconductor device and method for its manufacture |
US4249193A (en) * | 1978-05-25 | 1981-02-03 | International Business Machines Corporation | LSI Semiconductor device and fabrication thereof |
FR2443185A1 (en) * | 1978-11-30 | 1980-06-27 | Ibm | TOPOLOGY OF INTEGRATED SEMICONDUCTOR CIRCUITS AND METHOD FOR OBTAINING THIS TOPOLOGY |
JPS5712534A (en) * | 1980-06-27 | 1982-01-22 | Hitachi Ltd | Semiconductor device |
FR2495834A1 (en) * | 1980-12-05 | 1982-06-11 | Cii Honeywell Bull | INTEGRATED CIRCUIT DEVICE OF HIGH DENSITY |
JPS57186350A (en) * | 1981-05-13 | 1982-11-16 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS58112343A (en) * | 1981-12-26 | 1983-07-04 | Olympus Optical Co Ltd | Semiconductor and manufacture thereof |
JPS58143550A (en) * | 1982-02-22 | 1983-08-26 | Nec Corp | Semiconductor device |
JPS5943548A (en) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS59103455U (en) * | 1982-12-28 | 1984-07-12 | 富士通株式会社 | semiconductor equipment |
EP0113828B1 (en) * | 1983-01-12 | 1990-02-28 | International Business Machines Corporation | Master slice semiconductor chip having a new multi-function fet cell |
JPS59159558A (en) * | 1983-03-01 | 1984-09-10 | Toshiba Corp | Semiconductor substrate |
JPS63278249A (en) * | 1986-12-26 | 1988-11-15 | Toshiba Corp | Wiring of semiconductor integrated circuit device |
US5124776A (en) * | 1989-03-14 | 1992-06-23 | Fujitsu Limited | Bipolar integrated circuit having a unit block structure |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1064185A (en) * | 1967-05-23 | 1954-05-11 | Philips Nv | Method of manufacturing an electrode system |
DE1789138B2 (en) * | 1967-06-23 | 1976-12-09 | Ausscheidung aus: 17 65 632 RCA Corp., New York, N.Y. (V.St.A.) | LSI CIRCUIT BUILT UP FROM UNIT CELLS |
US3558992A (en) * | 1968-06-17 | 1971-01-26 | Rca Corp | Integrated circuit having bonding pads over unused active area components |
US3584269A (en) * | 1968-10-11 | 1971-06-08 | Ibm | Diffused equal impedance interconnections for integrated circuits |
US3656028A (en) * | 1969-05-12 | 1972-04-11 | Ibm | Construction of monolithic chip and method of distributing power therein for individual electronic devices constructed thereon |
US3621562A (en) * | 1970-04-29 | 1971-11-23 | Sylvania Electric Prod | Method of manufacturing integrated circuit arrays |
US3771217A (en) * | 1971-04-16 | 1973-11-13 | Texas Instruments Inc | Integrated circuit arrays utilizing discretionary wiring and method of fabricating same |
US3725743A (en) * | 1971-05-19 | 1973-04-03 | Hitachi Ltd | Multilayer wiring structure |
US3808475A (en) * | 1972-07-10 | 1974-04-30 | Amdahl Corp | Lsi chip construction and method |
-
1975
- 1975-04-22 CA CA225,413A patent/CA1024661A/en not_active Expired
- 1975-05-13 IT IT2325375A patent/IT1038108B/en active
- 1975-05-21 FR FR7516533A patent/FR2276693A1/en active Granted
- 1975-05-21 GB GB2187575A patent/GB1513893A/en not_active Expired
- 1975-05-26 DE DE19752523221 patent/DE2523221A1/en active Granted
- 1975-06-04 JP JP6665775A patent/JPS5125085A/en active Granted
- 1975-06-16 CH CH775675A patent/CH583970A5/xx not_active IP Right Cessation
- 1975-06-18 ES ES438666A patent/ES438666A1/en not_active Expired
-
1983
- 1983-10-20 JP JP19540983A patent/JPS5989435A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7317251B2 (en) | 2003-04-11 | 2008-01-08 | Infineon Technologies, Ag | Multichip module including a plurality of semiconductor chips, and printed circuit board including a plurality of components |
Also Published As
Publication number | Publication date |
---|---|
JPS5753984B2 (en) | 1982-11-16 |
IT1038108B (en) | 1979-11-20 |
FR2276693B1 (en) | 1977-04-15 |
CH583970A5 (en) | 1977-01-14 |
ES438666A1 (en) | 1977-03-16 |
DE2523221C2 (en) | 1992-09-17 |
JPS5125085A (en) | 1976-03-01 |
CA1024661A (en) | 1978-01-17 |
JPS5989435A (en) | 1984-05-23 |
FR2276693A1 (en) | 1976-01-23 |
DE2523221A1 (en) | 1976-01-15 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19940521 |