GB1586230A

GB1586230A - Semiconductor wafers for the production of highlyintegrated modules

Info

Publication number: GB1586230A
Application number: GB3967777A
Authority: GB
Original assignee: Siemens AG
Current assignee: Siemens AG
Priority date: 1976-09-27
Filing date: 1977-09-23
Publication date: 1981-03-18
Also published as: JPS5342578A; DE2643482A1; FR2365883A1; NL7710490A

Description

(54) IMPROVEMENTS IN OR RELATING TO SEMICONDUCTOR WAFERS FOR THE PRODUCTION OF HIGHLY-INTEGRATED MODULES (71) We, SIEMENS AKTIENGESELLSCH AFT, a German Company of Berlin and Munich, German Federal Republic, do hereby declare the invention, for which we pray that a patent may be granted to us, and the method by which it is to be performed, to be particularly described in and by the following statement : The present invention relates to semiconductor wafers for the production of highly-integrated modules.

In the production of highly-integrated modules for use in data processing and control systems, attempts to attain ever higher degrees of integration have led, because of the combination of a very large number of individual functions in a single module, to such specialised integrated modules that each module type can be used only at a few points or even at only one point of a larger functional unit. The result is the need to produce a large number of different types of component each only requiring to be supplied in small numbers. However, two processes have already been proposed, the object of which is to maintain the development costs and the time elapsing between the formulation of a particular user's requirements and the manufacture of a module to satisfy them within viable limits. In the first process, which is referred to under the name of the "Masterslice Principle" (see German Patent Specification as open to inspection No. 2,334,405, and Digest of the IEEE International Solid-State Circuits Conference 1974, pages 62-63), a standardisation diffusion pattern is used. In this process, diffusion is used to form a large number of transistors and resistors in a semiconductor wafer, which, apart from a few exceptions; are not initially connected to one another. In addition to edge zones provided with connection elements by means of which the integrated circuit module can subsequently be externally connected, the basic structure-of the wafer comprises a plurality of discrete surface portions which are arranged iri the form of a matrix and which are mutually spaced from one another. These surface portions, which are generally referred to as "cells", possesses identical, subbasic structures produced by diffusion. The basic structure is independent of the final design of the integrated circuit module. Consequently, the diffusion masks used to form the basic structure need only be set up once.

The diffused basic structure is supplemented by conductor paths formed at different levels with insulating intermediate layers between the paths at adjacent levels to form a specific circuit module. The intermediate layers are so designed that electrically conductive connections can be established between the diffused basic structure and the conductor paths at different levels themselves.

The design of the wiring of the integrated module takes place in two stages. The internal basic circuit of the cell which is evolved by the module manufacturer is so designed that simple logic-linking elements, such as NAND or NOR-gates, are formed from the contents of transistors and resistors provided in each cell. It is possible for the manufacturere to provide the user with more complex functional elements as basic circuits.

The user now prepares the logic design of the circuit which is to be integrated in the module and supplies this design and generally a list of the connections between the cells, to the manufacturer. With the help of this information, the manufacturer prepares the specifications for the overall wiring and finally puts the module into production.

In the second process which is already known under the name of the "Mosaic process" (see Electronic Design for 15.3.1970, page 42), the semiconductor wafer similarly comprises a plurality of individual surface portions. However, the individual surface portions are in this case generally of different sizes and have different diffused basic structures. These basic structures and the associated wiring for the formation of specific functional units are previously designed by the manufacturer and stored in a computer library. The user can freely select the functional units he requires, such as for example flip-flops, multiplexers, counters and the like, and then informs the manufacturer of the arrangements and connections which he requires. He is thus able to proceed in a similar fashion to that followed in the handling of medium scale integrated circuits.

The application of principles outlined above to the development of integrated modules having a high degree of integration does indeed basically produce a considerable reduction in time and cost, in comparison with the development of a speialised integ- rated module, although as a rule, only a lower packing density can be achieved. This becomes particularly clear, if irregularly structured logic control circuits are functionally closely connected to regularly constructed storage circuits, registers and the like in a circuit arrangement which is to be integrated.

The separation into modules for logic-linking circuits and modules having storage functions which may be carried for this reason results in more interfaces which in turn gives rise to the need for connection lugs, larger housings and more output drive devices.

It is an object of the present invention to provide a semiconductor wafer by the use of which the packing density can be increased of modules having a high degree of integration.

According to the invention there is provided a semiconductor wafer for use in the production of highly-integrated modules having a basic structure formed by diffusion, comprising a peripheral zone having connection elements formed therein for external connection of a circuit formed in said wafer, and a plurality of semiconductor components arranged to form a plurality of individual cells located in a portion of the surface of said wafer within said peripheral zone, each said cell having a sub-basic diffused structure, a majority of said cells having identical subbasic structures and surface areas and the or each of the remaining cells having a sub-basic structure which is different from that of said majority of the cells, and a surface area which is greater than that of each individual one of said majority of cells. The basic structure of the modules (and thus of the sub-basic structures) will normally consist of transistors and resistors.

A preferred form of wafer according to the invention is one wherein the majority of cells having identical sub-basic structures are arranged in the form of a matrix mutually spaced from one another, and are provided with conductor paths for the formation of predetermined sub-basic circuits from the transistors and resistors of each sub-basic structure within the individual cells, and for the formation of an overall circuit composed of the basic sub-circuits in accordance with given requirements; and wherein the or each of the remaining cells has a different subbasic structure, the sub-basic structure of the or each remaining cell and the wiring pattern which is required to form a basic circuit therefrom being freely selectable from one or more different basic sub-circuits to meet a particular requirement.

The invention will now be further described with reference to the drawing, which is a schematic plan view of a semiconductor wafer according to the invention.

Referring to the drawing, a semiconductor wafer 1 is provided with an edge zone 2 which contains connection elements for subsequent connection of conductor paths forming internal connections to outwardly-directed connection pins on the finished module and output drive device. The region of the surface of the semiconductor wafer 1 which lies within the edge zone 2 is provided with a plurality of surface portions or cells mutually spaced from one another. A majority of these cells 3 are arranged in the form of a matrix and these cells all have the same dimensions.

The cells 3 also have identical, diffused subbasic structures, i.e. the number of transistors and resistors and their geometrical arrangements are identical in all the cells 3. The remaining cell 4 is larger than any of the cells 3 and has a different diffused sub-basic structure. The diffused sub-basic structure of the cell 4 is usually such that it is particularly suitable for forming a store complex or a data register. By the provision of suitable internal wiring of the cells using conductor paths at different levels (not shown), the diffused subbasic structures of the cells are transformed into basic sub-circuits. Fundamentally there are two different ways of carrying out the internal wiring of the cells 3. In one method (which is already known for this general purpose) all the cells 3 are connected in the same way to form simple logic-linking elements, such as AND-gates or NOR-gates.

It has already been proposed to provide different, pre-designed internal cell wiring patterns so that the user can have complex basic circuits made up of two or three cells for the logic design of the circuit to be integrated. For the cell 4 it is also possible to provide a variety of different possible wiring patterns which, even with the same diffused basic sub-structure, allow specific variations of the basic circuit of this cell to be achieved.

Thus, for example, when the cell 4 is to be used as a store complex, by changing the wiring pattern it is possible to alter the external organisation of the store complex within certain limits with respect to the number of words, or of bits per word. In place of a storage complex, other enclosed circuit complexes can be formed', in which case it will generally be desirable to adapt the diffused basic sub-structure to the particular use. More than one remaining cell corresponding to the cell 4 can, if desired, be accommodated in the semiconductor wafer 1.

WHAT WE CLAIM IS: 1. A semiconductor wafer for use in the

**WARNING** end of DESC field may overlap start of CLMS **.

Claims

**WARNING** start of CLMS field may overlap end of DESC **. arrangements and connections which he requires. He is thus able to proceed in a similar fashion to that followed in the handling of medium scale integrated circuits. The application of principles outlined above to the development of integrated modules having a high degree of integration does indeed basically produce a considerable reduction in time and cost, in comparison with the development of a speialised integ- rated module, although as a rule, only a lower packing density can be achieved. This becomes particularly clear, if irregularly structured logic control circuits are functionally closely connected to regularly constructed storage circuits, registers and the like in a circuit arrangement which is to be integrated. The separation into modules for logic-linking circuits and modules having storage functions which may be carried for this reason results in more interfaces which in turn gives rise to the need for connection lugs, larger housings and more output drive devices. It is an object of the present invention to provide a semiconductor wafer by the use of which the packing density can be increased of modules having a high degree of integration. According to the invention there is provided a semiconductor wafer for use in the production of highly-integrated modules having a basic structure formed by diffusion, comprising a peripheral zone having connection elements formed therein for external connection of a circuit formed in said wafer, and a plurality of semiconductor components arranged to form a plurality of individual cells located in a portion of the surface of said wafer within said peripheral zone, each said cell having a sub-basic diffused structure, a majority of said cells having identical subbasic structures and surface areas and the or each of the remaining cells having a sub-basic structure which is different from that of said majority of the cells, and a surface area which is greater than that of each individual one of said majority of cells. The basic structure of the modules (and thus of the sub-basic structures) will normally consist of transistors and resistors. A preferred form of wafer according to the invention is one wherein the majority of cells having identical sub-basic structures are arranged in the form of a matrix mutually spaced from one another, and are provided with conductor paths for the formation of predetermined sub-basic circuits from the transistors and resistors of each sub-basic structure within the individual cells, and for the formation of an overall circuit composed of the basic sub-circuits in accordance with given requirements; and wherein the or each of the remaining cells has a different subbasic structure, the sub-basic structure of the or each remaining cell and the wiring pattern which is required to form a basic circuit therefrom being freely selectable from one or more different basic sub-circuits to meet a particular requirement. The invention will now be further described with reference to the drawing, which is a schematic plan view of a semiconductor wafer according to the invention. Referring to the drawing, a semiconductor wafer 1 is provided with an edge zone 2 which contains connection elements for subsequent connection of conductor paths forming internal connections to outwardly-directed connection pins on the finished module and output drive device. The region of the surface of the semiconductor wafer 1 which lies within the edge zone 2 is provided with a plurality of surface portions or cells mutually spaced from one another. A majority of these cells 3 are arranged in the form of a matrix and these cells all have the same dimensions. The cells 3 also have identical, diffused subbasic structures, i.e. the number of transistors and resistors and their geometrical arrangements are identical in all the cells 3. The remaining cell 4 is larger than any of the cells 3 and has a different diffused sub-basic structure. The diffused sub-basic structure of the cell 4 is usually such that it is particularly suitable for forming a store complex or a data register. By the provision of suitable internal wiring of the cells using conductor paths at different levels (not shown), the diffused subbasic structures of the cells are transformed into basic sub-circuits. Fundamentally there are two different ways of carrying out the internal wiring of the cells 3. In one method (which is already known for this general purpose) all the cells 3 are connected in the same way to form simple logic-linking elements, such as AND-gates or NOR-gates. It has already been proposed to provide different, pre-designed internal cell wiring patterns so that the user can have complex basic circuits made up of two or three cells for the logic design of the circuit to be integrated. For the cell 4 it is also possible to provide a variety of different possible wiring patterns which, even with the same diffused basic sub-structure, allow specific variations of the basic circuit of this cell to be achieved. Thus, for example, when the cell 4 is to be used as a store complex, by changing the wiring pattern it is possible to alter the external organisation of the store complex within certain limits with respect to the number of words, or of bits per word. In place of a storage complex, other enclosed circuit complexes can be formed', in which case it will generally be desirable to adapt the diffused basic sub-structure to the particular use. More than one remaining cell corresponding to the cell 4 can, if desired, be accommodated in the semiconductor wafer 1. WHAT WE CLAIM IS:

1. A semiconductor wafer for use in the

production of highly-integrated modules having a basic structure formed by diffusion, comprising a peripheral zone having connection elements formed therein for external connection of a circuit formed in said wafer, and a plurality of semi-conductor components arranged to form a plurality of individual cells located in a portion of the surface of said wafer within said peripheral zone, each said cell having a sub-basic diffused structure, a majority of said cells having identical subbasic structures and surface areas and the or each of the remaining cells having a subbasic structure which is different from that of said majority of the cells, and a surface area which is greater than that of each individual one of said majority of cells.

2. A semiconductor wafer as claimed in Claim 1, wherein the basic structure of said modules consists of transistors and resistors.

3. A semiconductor wafer as claimed in Claim 2, wherein the cells of said majority having identical sub-basic structures are arranged in the form of a matrix mutually spaced from one another, and are provided with conductor paths for the formation of predetermined sub-basic circuits from the transistors and resistors of each sub-basic structure within the individual cells, and for the formation of an overall circuit composed of the basic sub-circuits in accordance with given requirements; and wherein the or each of said remaining cells has a different subbasic structure, the sub-basic structure of the or each said remaining cell and the wiring pattern which is required to form a basic circuit therefrom being freely selectable from one or more different basic sub-circuits to meet a particular requirement.

4. A semiconductor wafer substantially as hereinbefore described with reference to and as schematically illustrated in the drawing.

5. A highly-integrated module produced using a semi-conductor wafer as claimed in any one of Claims 1 to 4.