JPS5954255A - Large scale integrated circuit - Google Patents

Abstract

PURPOSE:To implement an LSI in a short time, by arranging exclusively designed special function blocks at appropriate positions on a cell array substrate, on which basic cells are arranged in an mXn pattern. CONSTITUTION:A chip 1 has an array structure, wherein basic cells 2 are fundamentally arranged in an mXn pattern. The cells can be arranged so that the number of the cells is freely increased or decreased. Function blocks 3 are arranged depending on the purpose regardless of the restriction imposed by a foundation. Then, the function blocks having a systematic structure such as memories and special purpose blocks such as buffers are arranged at the appropriate positions. The memories are exclusively designed, with the basic structure of the cell array suitable for computer aided design as a fundamental form, and has excellent area efficiency. Then, the special function peculiar to the kind of the device is satisfied without nullifying the features of the cell array substrate, and the LSI can be implemented in a short time.

Description

[Detailed description of the invention] [Technical field to which the invention pertains] The present invention relates to large scale integrated circuits.

[Prior art]

A conventional circuit is constructed on a cell array substrate in which basic cells are arranged in an In.times.n pattern.

For this reason, a cell array structure has been put into practical use as a method for shortening the design period for large-scale integrated circuits.

However, in conventional large-scale integrated circuits, all the circuits that make up the logic circuit are laid out in a layout of basic cells, and they have a regular structure such as memory. (Regamma ridges and blocks had the disadvantage of being poor in terms of area and performance.

[Purpose of the invention]

An object of the present invention is to provide a large-scale integrated circuit that can achieve the same improvements in area and performance.

In other words, the purpose of the invention is to create a ROM with good dX angle 1 and 4
几Aht 1 rule counterfeit blocks or υ, placement performance-oriented % special purpose blocks, etc. can be freely scattered as functional blocks on the cell array base without being constrained by the cell array according to the purpose. The goal is to provide a program that satisfies the special functions required by the transfer and can be put into practice in a short period of time.

[Configuration of the Invention a] The large-scale integrated circuit of the present invention is constructed by disposing at least one specially designed special functional block on a cell array base material in which return cells are arranged in mxn.

In other words, the functional blocks of regular structures such as area-efficient memories, buffers, etc., which are specially designed based on the basic structure of the cell array described in the ``large-scale circuits of the present invention'' and the ``comprehensive design'', or buffers, etc. By making it possible to place special purpose blocks, etc., as functional blocks,
It is constructed so as not to destroy the characteristics of the cell array board and to satisfy the special functions required for each type of product.

[Explanation of Examples]

Next, embodiments of the present invention will be described in detail with reference to page 1 of 1.

Figure 1 is a top view showing one embodiment of the present invention.
In the large integrated circuit shown in the figure, the chip 1 basically has basic cells 2 in an m x n array structure, which can be freely increased or decreased, and the functional blocks 3 are bound by the underlying constraints depending on the purpose. It is placed frequently.

As a result, a single device using area-efficient function blocks with a regular structure, such as a memory, can have a small chip size.

FIG. 2 shows another embodiment of the present invention in the diagram 7f<i.tau.111.

In the integrated circuit shown in Figure 2, the chip 1 consists of basic cells 2 arranged in an array structure f6, and an m-bit RAM in one corner of the chip 1. There is.

By placing both the number of hits, the number of basic cells, and the position of this tF multiblock 3RAM, a master slice structure is obtained.

Therefore, it can be used for many purposes by including R, A, and M, and by using 2- and 2- as master slice gangsters, both the design period and the construction time can be shortened.

[Effect of Departure JJ]

The large-scale P-year circuit of the present invention is often constrained to the base 4\← array and punishes the n1! block.

Depending on the position, the effect of the mechanical reinforcement ffi+ may be reduced, the facet vertebrae may be reduced, or the purpose If: , n: (
This has the advantage that it is possible to realize a built-in circuit.

Figure 1 is a top view showing an embodiment of the present invention.

1...Chisso, 2...Basic cell, 3...
...1-block with machine.

Representative Bengoshi Susumu Uchihara

Claims (1)

[Claims] An Ip8 circuit characterized by having at least one specially designed special functional block arranged on a cell array substrate in which basic cells are arranged in m x n.