DE2643482A1 - SEMI-CONDUCTOR PLATE FOR MANUFACTURING HIGHLY INTEGRATED COMPONENTS - Google Patents

Description

SIEMENS AKTIENGESELLSCHAFT ■ Our symbol Berlin and Munich VPA 76 P 2 1 6 3 BRD

Semiconductor wafers for the production of highly integrated components.

The invention relates to a semiconductor wafer according to the preamble of claim 1.

The endeavor in the production of integrated modules for use in data processing and control systems Achieving ever higher degrees of integration leads to special functions as a result of the combination of a large number of individual functions Integrated modules that each module type in a larger functional unit only in a few places or only in one place can be used. The result is a great variety of types with small piece counts for the individual type. However, there are two Processes have become known that have the goal of reducing the development effort and the time between the receipt of a special user request and to keep the completion of a building block within tolerable limits. With the first, even under the process known as the "Masterslice principle" (cf. DT-OS 2 334 405, Digest ot the IEEE International Solid-State Circuits Conference 1974, pages 62-63) is from a standardized diffusion pattern assumed. A large number of Transistors and resistors are formed which, apart from a few exceptions, initially have no connection to one another to have. This basic structure has, in addition to edge zones with connection

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elements for the subsequent production of the connections of the integrated Switching mechanism to the outside a number of discrete, matrix-like arranged surface sections with mutual distances on. The surface sections referred to as cells have identical diffused partial basic structures. The basic structure is independent of the final version of the integrated switching mechanism. As a result, those who determine the basic structure must also Diffusion masks can only be created once.

The diffused basic structure becomes a special switching mechanism through interconnect layers with insulating intermediate layers added. The intermediate layers are designed so that conductive connections between the diffused basic structure and the interconnect layers or between the interconnect layers themselves can be produced. The design of the wiring of the integrated Module takes place in two stages. The cell-internal basic circuit developed by the module manufacturer is designed in such a way that that from the supply of transistors and resistors in each cell, simple logic elements such as NAND or NOR members arise. There is also the possibility that the manufacturer can provide the user with more complex functional elements as basic circuits.

The user now creates the logical design of the switchgear that is to be integrated in a module and supplies this and usually a list of the connections between the cells to the manufacturer. On the basis of this information, the manufacturer creates the documents for routing the entire wiring and finally manufactures the module.
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In the second process, which is also known as the "mosaic process" (compare Electronic Design, March 15, 1970, Page 42) is known, the semiconductor wafer is also divided into individual surface sections. The individual area sections However, they now mostly have different sizes and different diffused basic structures. These basic structures and the associated wiring to form certain functional

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units are pre-developed by the manufacturer and integrated into a Computer library saved. The user can use the functional units, such as flip-flops, multiplexers, counters and the like freely and the arrangements desired by him and specify connections to the manufacturer. So he is able to proceed in a similar way as he is is used to handling integrated modules with a medium degree of integration.

ΊΟ The application of the principles described in the development Integrated modules with a high degree of integration bring considerable time and cost savings compared to development of a special integrated module from the ground up, but usually only a lower packing density can be achieved with it achieve. This becomes particularly clear when irregularly structured logical ones in a switching mechanism to be integrated Control circuits with regularly structured memory circuits, registers and the like are functionally closely connected are. For this reason, the separation into building blocks for logic gating circuits and Modules with memory functions result in more interfaces, which in turn means more terminal lugs, larger housings and more more output drivers conditionally.

It is the object of the invention to specify measures for increasing the packing density of components with a high degree of integration for the realization of switchgear with irregular structured parts, in particular logical combination circuits and with regularly structured parts, e.g. B.

Memory circuits.

Based on a semiconductor wafer according to the generic term of claim 1, this object is achieved by the features in the characterizing part of claim 1. One Another solution results from the features of claim 2.

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The invention is illustrated below with reference to in the figure Embodiments described in more detail. 1 shows the diagram of a first distribution of partial areas the semiconductor die and

2 shows the diagram of a second distribution of partial areas on the semiconductor wafer.

Figure 1 shows a semiconductor wafer 1 with an edge zone 2, which connection points for the later connection of the internal Contains interconnect layers with the terminal lugs leading to the outside of the finished module and output driver. The inside the edge zone 2 lying area of the semiconductor wafer 1 is divided into several surface sections or cells with mutual Divided at intervals. Some of these cells are arranged like a matrix and have the same dimensions. The cells moreover have identical diffused basic structures, i. H. the supply of transistors and resistors and their geometric arrangement is the same in all cells 3. Cell 4, which is generally larger, is an exception as cell 3. For this reason alone, but not only therefore, the cell 4 contains a different diffused basic structure. The diffused basic structure of the cell 4 will generally be designed to be optimal for the formation of memories or data registers. Through internal Wiring of the cells with the aid of interconnect layers, the diffused basic structures are supplemented to form basic circuits. For the internal wiring of the cells 3 are basically two different options. The one, well known Possibility provides all cells 3 in the same way with simple logic elements, such as AND or NOR elements occupy. It has also been suggested by the provision of various pre-engineered in-cells Wiring patterns provide the user with the logical design of the complex basic circuits to be integrated ·, which occasionally can also comprise two or three cells. Different can also be used for cell 4 Wiring patterns can be provided that are also used with a

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constant diffused basic structure still allow certain variations of the basic circuit. For example when using the cell 4 as a storage complex by changing the wiring pattern within certain limits external organization of the memory complex with regard to the number of words or bits per word can be changed. Instead of of a memory field, other self-contained circuit complexes can also occur, in which case it is generally expedient will be to adapt the diffused basic structure accordingly. A plurality of cells corresponding to the cell 4 can also be accommodated on the semiconductor wafer 1.

The division of the surface area shown schematically in FIG. 2 on the semiconductor wafer 5 within the edge zone 6 is based on the already mentioned mosaic process. The cells 7 are in general not only of different sizes, they also have and require different diffused basic structures thus also different cell-internal wiring patterns for the production of the basic circuits. The basic circuit are pre-developed by the semiconductor manufacturer and can be freely selected by the user according to the needs identified by him to get voted. In the case of complex switching mechanisms to be integrated, the case may arise that very irregular, rarely occurring or logic circuits are required to supplement the pre-developed basic circuits, for this purpose some further cells 8 are provided on the semiconductor wafer 1. These further cells 8 have an identical one Partial basic structure. They therefore correspond to a partial area of a master slice semiconductor wafer. The wiring inside the cell is also uniform and designed in such a way that 8 simple basic links from the component stock of each cell, how NAND or NOR elements are formed. These basic links can then be with each other or with the basic circuits in cells 7 can be combined as required.

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Claims (2)

Claims (Λ . \ Semiconductor platelets for the production of highly integrated modules with a basic structure formed by diffusion from transistors and resistors, which basic structure in addition to edge zones with connection elements for the production of connections to the outside of the switching mechanism to be integrated in the module, a plurality of identical, spaced apart in a matrix-like manner Has surface sections with identical partial basic structures, with interconnect layers for the formation of pre-developed basic circuits from the supply of transistors and resistors within the individual surface sections and for the formation of a special overall circuit from the basic circuits according to the respective requirements, characterized in that at least one further surface section (4 ) is provided with deviating the sub-basic structure and that the sub-basic structure and the wiring pattern required to form a basic circuit from one or from a plurality of regarding I of the basic structures and wiring patterns pre-developed different basic circuits can be freely selected. 2. Semiconductor wafers for the production of highly integrated building blocks with a basic structure formed by diffusion from transistors and resistors, which basic structure next to Edge zones with connection elements for the production of connections of the switchgear to be integrated in the module outwardly a number of generally unequal, spaced-apart surface sections with im generally has different sub-basic structures, with interconnect layers for the formation of pre-developed basic circuits from the supply of transistors and resistors within the individual surface sections and to form a special overall circuit from the basic circuits according to the respective requirements, thereby marked net that some other surface sections (8) with one another -7- ■ 809813/0397 INSPECTED . ^ 76 P 2 1 6 3 FRG others are the same and generally differ from the basic sub-structures of the remaining surface sections are provided and that the formation of simple linking elements within the individual further surface sections (8) the various wiring patterns required are uniformly and firmly specified. 809813/0397