DE2332772C2 - Circuit arrangement for the priority-dependent release of devices to which different priorities are assigned for inclusion in data transmission processes - Google Patents

Description

b5 F i g. 1 shows the connections or busses

the in F i g. 3 circuit arrangement shown, which as

Priority network interconnection circuitry

The invention relates to a circuit arrangement. For the purpose of illustration

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8 devices N to N + 7 are shown in FIG. 1 as being connected, which means that the input of the is shown. Egg. However, it should be understood that the first device (each device can have more than eight devices in this. Example has only one input) would be connected directly to Schalturigser · Dk with regard to the busbars shown. The lines indicated by the earth signal are used for connecting or connecting devices. 5 Error status b / w. The zero state would be the first few electronic isolating circuits (inclusion direction indicating that it has the highest priority, lent to the priority combinatorial circuit) of the various Nu'lstatus to which can be two-order. The facilities can be forwarded to printer, th facility, or regenerated. Storage devices such as tape and disk units, 10 although the second device does not include access to the etc. Each device contains five bus connections, the null state would be to the connection or terminals A through E, which are forwarded to their priority device, etc. Each logic circuit connections are assigned. Whenever the zero state is supplied by a device connection A supplies the output signal or the priority, a logic circuit delay display of the priority logic circuit or the delay time is introduced. So there are thirty facilities -logic of the respective facility; the connections B to E are connected to the collecting line and the connection is the input connections of the connecting linkage circuit delay time for each device connection circuit. There are four input signals in the order of magnitude of 10 nanoseconds as an example, so conclusions B to E would be shown. These four input signals take about 300 nanoseconds until the last inclusions or inputs enable the associated direction to determine whether it can get access to the collecting device, the priority display from four previous directions. Will be recorded with the 2-establishment facilities. So checks z. B. the review feature worked, this time would be on! Device N + 5, the priority display or the off about 150 nanoseconds halved, and if more than * jjangssignal at terminal A of devices N + 1 to a 4-device review -Feature detected by J7V + 4. This is referred to here as the "looking back feature" if the time span were about 75 nanoseconds. This means that each device knows whether, within which the priority display relates to the [Vie access to a processing device or central unit CPU connected to the bus, as shown in FIG. 3, via device would spread.

Obtaining data paths of the bus (not shown). B. with regard to Fig. 1, the ge of the four preceding devices makes. Device Nan each of its input connections Abis In the course of the further explanation it should be noted that the E carry a voltage level, which can be a circuit earth for the system using the present invention and which reflects the zero state for the purpose of the "priority bus" for the priority network explanation Thus, each device at this device N is connected to the zero state at each of its inputs bus and also determines and knows (as can be seen in detail below, data bus (not shown) for data paths) that it is being created receives access to the trunk, which the devices can process with one at a time. The priority indicator on the output antenna device at one end of such a connection A of device N is connected to the input antenna trunk. If a device has a connection B. C, D and E of facilities N + 1 , N + 2, has to gain access to the manifold, N + 3 or N + 4 can effectively be viewed at the same time, what should be viewed, the facility in question. The device N + 1 also receives the zero information, including its identification, transmitted to its input terminals C, D and ff via the data bus and at the same time that the device processing device outputs it. In addition, the device, which picks up on to E with regard to its position, can control the zero state at its input connections B. The relevant zero state is most dense in the processing device at which it is present at the input connections D and E of the device manifold (the expression manifold N + 2 as well as at the input connection £ of the device is used here to denote the device N + 3 as well at the same point in time recorded priority bus as the data bus, at which it is used at input connections B to E of the device), the facility with the highest priority facility N is included,
Each device simultaneously delivers its priority priority on the connection direction of the priority lists on the basis of the signal status at its connection circuit of the respective device in relation to connections. Accordingly, the device receives the location of the processing device with respect to 55 N + 4 the priority indication at the terminal A of each of the one end of the bus. It should be possible to use the devices N to N + 3 at the same time that the rear viewer of the invention is on point. {Each priority display of this type requires only two devices that can be expanded, such as logic circuit delay time. Since this will be described in more detail elsewhere. Priority notifications are carried out in parallel, however, the review feature can also be extended to more than 60 including for all four facilities connected to the bus line, such as B. to eight devices, from nen devices only one logic circuit can be expanded. Delay time introduced. Requires z. B. no on-By the look back feature, the time direction of the facilities N to N + 3 to access is reduced, the priority display of the respective one of the bus, so their priority displays are directed for the propagation on the bus. it each appear as zero status displays, while that requires the priority network z. B. light the de at the same time at the input connections review feature, the first device B to £ of the device N + 4 would be included. The one priority display, which only has an earth signal, its facility N + 4 accordingly knows after only one

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logic circuit delay time so that each of the signals received at the connections BC D and E of the access to the bus line can be obtained when the signals picked up by the OR gate 12-4 in the zero-C are ready to do so. If, however, one of the priority displays was in the state, the device priority signal of the devices Λ / to N + 3 in the "!" State, which also occurs in the zero state, whereby the change was shown that one of these devices was ready to display 5 direction W + 4 becomes that it was to get access to the bus so bus can get. The readiness signal, which would indicate the readiness of the facility Λ / + 4 after already being set up. occurs in the logic circuit delay time to know that it is 1-state (here it is assumed that the disconnector can gain access to the bus.

In the following it is particularly important to refer to Fig. 3 input terminal of the OR gate 12-5 is supplied); gen, in which a typical priority display logic or thus the device Λ / + 5 is indicated that a -linking circuit for the facilities / V + 3 up to the previous facility access to the collecting point-Λ / + 5 is shown. and that it, namely the facility

In this case, the output logic element Λ / + 5, the device N + 2 and the input logic 15 can not get access to the bus. The 1 state with which the readiness of the member of the device Λ / + 6 is shown. The readiness signals indicating the device Λ / + 4 each have an input OR element 12 with entry, thus being planted with each of the subsequent input connections ¹ RC ₁ D and E The OR elements 12 directions / V + 5 to N + 7 continue, are each with their output at an input of a Thus it should be apparent that the response time of the

OR gate 14 connected; In addition, the respective priority network outputs a device priority signal with regard to the determination or the temporary OR element 12 to the associated circuit determination of the device, the access to the collective device. The line to get has decreased by a factor, output signa! of the OR gate 14 can be fed directly to the next device depending on the extent of the review of the Priontatsein input (connection B) of the OR gate 12 of the display of the preceding or following devices, or it can depend. In addition, each device not only preferably has to be fed to an AND gate 16, priority indicators of the (e.g.) four preceding which is included in the circuit whereby a device is received, but also knows the ever-erase priority feature which is introduced below the respective facility at the same time the priority display will be explained. The OR element 14 is connected to all of the preceding devices in such a way that at its other input it picks up the readiness element 12 of the device in question indicating the readiness of the OR device in the base of the four input signals, and that can also be taken from the associated. This results from the fact that the priori circuit of the device concerned. notifications of all previous institutions

Typical for the associated circuit, which is shown in the priority display of such four immediately above With regard to the facility priority signal and that of the previous 35 facilities. Ready signal indicating readiness for installation After the identification (via lines of the

has been specified, the manifold (not shown) is the circuit described in the other place. In signal, the device priority that has received access to the busbar shows, in a few words, the device coming into question for the processing device or central unit CPU on the basis of the 40 10 recorded. in such a way that z. For example, the input signal recorded by the processing-OR element 12 produces neither a zero state nor a 1 state with regard to such an input. On the basis of their identification can begin, the display of the zero status, the relevant input, the priority network can release itself or jo-

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meline can have. Address 45 directions when the 1 state is present. Without the AND gates 16, the device in question is indicated that it and the delete priority signal. that cannot gain access to the manifold from the processor. This last-mentioned case means that a previous identification of the device that previously wanted an outgoing device of higher priority has received access. such access needs to be obtained. The ready signal, which indicates the device ready 50 the priority network for a noticeable time for its readiness. that release or deletion. This means that: has the device in question is ready to give the first device in a system independent access to the bus; therefore, from the presence or absence of a jerk signal, the relevant signal occurs in the 1 state. If the concerned person has access to the bus and was thus a fending device not ready for such an access, 55 1-state signal from terminal A of the relevant, the signal occurs in a zero state. Facility submitted, which state of affairs.gnal to

The connections between the OR gates 12 and that of the last device were propagated in ei-OR gates 14 (assuming that without a system comprising 30 devices, the thirty-AND gate 16 is operated, with the output - times the 10 nanosecond delay time per Em connection of the logic elements 14 of the Α connection ω direction (that is about 300 nanoseconds) required) in F i g. 1 shown; on the connection in question borrowed from the 1 -state to the 0 -state of the membership will not be discussed further. However, it is indicated to go over to the respective institution, woz. For example, suppose that device N + 4 is ready for access to the bus by the priority indication of the respective device. Accordingly occurs is deleted. This does not apply regardless of the presence or absence of the foam-back feature indicating the readiness of this device, since the riding signal is in the 1 state. It should also be angenom- change from the 1 state in dtt zero state depending Prionmen that the means N to N + 3 are not willing tätsanzcige of each device is dependent on for access to the bus. Accordingly! such a change of state of the relevant

Establishment immediately preceding establishment.

Accordingly, in order to reduce the amount of time required to clear the priority network AND elements 16 in the priority logic of the respective Establishment introduced. The erase priority signal is fed to one input of the AND gates 16. This delete priority signal is generated after the device that is currently accessing the Bus has received its address is locked or locked, which means that the Address for addressing the memory associated with the processing device 10 is stored.

The generation of the erase priority signal has the effect that the output signal at terminal A of AND gate 16 changes to the zero state. Since each device receives the delete priority signal with its AND gates 16, the output signal of the device, db the priority display, changes to the zero state within a minimal period of time. In the course of the further explanation it is assumed that the erase priority signal is normally in the! State, whereby the signal state at the output of the OR gates 14 for transmission to the connections B, C, D and E of the OR gates 12 of the subsequent four bodies is released. If the priority network is to be deleted, the delete priority signal changes to the zero state only for the period of time that is necessary to ensure that the output signal of the OR gates 12 is also -r., Zero state Time span for the deletion of the network depends on how quickly the output signals of the OR gates 1 can be brought into the zero state. In summary, it can thus be stated that the total time available for the next device to gain access to the bus is determined by the time period for deleting the priority network plus the time period. which is required for the next device in order to record its identification in the processing device 10.

In certain cases, some parts of the trunk of the priority network are not used, either because a facility has been left out of the system, or because a facility for that priority point is planned in the future, or possibly because the electronic disconnect circuit which is actually in physical proximity to the bus at the point or position in question comprises sufficient electronic circuit so that double-sided circuit boards of electronic circuits are plugged in at one point, thereby preventing the exploitation of an adjacent point with regard to the non-utilization of a point of the bus, it should also be noted that the point in question can be a facility that is used by a facility that is not connected to the priority network. as it was originally intended, and without having to use additional electronic circuitry, it has been found that only an electrical connection or a short connecting wire is required as a single element, the connecting wire in question being connected between terminals A and B of the relevant connection point, which is empty or contains a logic circuit or logic which the priority network does not use

Referring to FIG. 2 it should be noted that the positions or positions for the facilities Λ / + 1, N + 2 and Λ / + 6 as empty bz '. not shown. This illustrates that adjacent positions or locations as well as separate locations on the bus can be empty, which means that an electronic separator circuit of a device which contains the priority logic is missing at the respective locations. Accordingly, the logic element 16 connected to the output connection A controls the connection elements belonging to the connections B, C and the device N + 3 , the connection elements belonging to the connections C, D and £ of the device N + 4, the connection elements belonging to the connections D and £ f of the device N +5 associated logic elements and the terminal E of the device N + 6 associated logic elements, v / enn the position Λ / + 6 is not empty. Accordingly, the device Λ / would have the highest priority and the device N + 3 would have the next higher priority, etc. Incidentally, the fact that there are three spaces does not slow down the response of the system. The output signal at terminal A of device N is z. B. received from the input terminal £ of the device N + 6 at the same time at which the output signals at the terminals A of the devices N + 3, N + 4 and N + 5 are received at the terminals B, C and D of the device N + 6 . Accordingly, if device / V + 6 were included in the system, it would know whether it could gain access to the bus just as quickly as device N + 4 would become aware of it if the devices N + were to gain access to it ί and N + 2 related digits would not be empty.

Depending on the number of vacancies on the manifold, no further control current or no further load is introduced. B. the logic element 16 of the device N require a sufficient load control capability for four loads or load resistances. This means that four load resistances would be introduced through the four logic elements 12 which are assigned to the devices N + 1 to N + 4. With two vacancies for the devices N +1 and N + 2 and assuming that the position N + 6 is not vacant, four equal loads or load resistances are also introduced. The load resistances are those load resistances that are assigned to the OR gates 12 of the devices N + 3 to N + 6. This means that even if the number of input signals supplied by the signal at the terminal A of the device N is increased from four to nine, the number of loads or load resistances remains at four. The reason for this is that those used Logic elements 12 are those of the transistor-transistor logic type or equivalents of this type of connection in which only a base current is required for the respective activation. In this example, in which the OR gates 12 of the devices N + 3, N + 4 and N + 5 receive more than one input signal from the terminal A of the device N , the OR gate 12 of such a device thus only requires a fixed current or base or base current for activation. Accordingly, the current consumption with regard to the logic element 16 of the device N is not increased. By adding a connecting wire between terminals A and B to a space, the line connected to the Α terminal is also made

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I line controlled, which avoids interference problems
I am. 35 ! ■ -
Y · I For this purpose 2 sheets of drawings IO 40 "'- i * ■ 1 45 • i Yo 50 SS I ■ ''^■; i · ■■■ -. · '. ^:: '. 60 [
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Claims (6)

1 2 tion. as indicated in the preamble of claim I. A priority system is already known to KS (»IBM, 1. Circuit arrangement for the priority-dependent Technical Disclosure Bulletin ". Vol. 12, No. I ₁ June 1969, release of facilities that have different ■> Page 75), in which the existing facility priorities are assigned in each, for an inclusion only the priority display of the facility in data transmission processes, with each F.inrirh - no higher priority is taken into account. This generates a device priority signal, which, however, indicates that with the relevant known priority it indicates whether the relevant device is to be included in the data transmission system in the corresponding priority displays. with each one in turn guiding the further facility from facility to facility upon its release for processing! will. It follows from this, however, that the response rate of a data transmission process emitting an active speed of the relevant known priority system signal at a display signal output is only relatively low. and each device that is involved in a data transfer process is also involved for the duration of the 15 ("Electronics" of December 21, 1970, pages 47 to 52; processing of the relevant data transfer US-PS 34 73 155). The simple and cheap electrical process remains approved, thereby using characteristic circuits, in which, however, the distinguishes that each device (e.g. N + 5) with response speed, ie the speed, with a logic element (e.g. 12- 5). which the one priority determination is made generates an individual device priority signal, indirectly depends on the number of devices, on the display signal outputs (A) of a given access to data processing devices 1 a plurality (e.g. 4) of institutions (Λ / + 4, to try to get. This means that in these- N + 3, N + 2, N + 1) is connected directly, which in this case the priority determination in a serial manner towards the institution concerned (N + 5), which is why this is also the case with these known systems successively higher priorities are assigned. 25 the same disadvantage is present as it is in the context of and that for the duration of the development of a context with the known at the outset 'Data transmission operation a blocking signal priority determination system has been specified. (Erase priority signal) in each device (z. B. The invention is now based on the object of a Λ / + 5) a locking device (z. B. AND gate circuit arrangement of the type mentioned so 16-5), which is to be formed in front of the display signal output (A) , that in the case of the priority-dependent release is switched, is supplied so that the display signal of to be included in data transmission processes Ie of all facilities (Λ / + 5, / V + 4, / V + 3, etc.) facilities not only those with regard to priority become inactive. previous institution is taken into account. 2. Circuit arrangement according to claim 1, but rather a predetermined plurality of soldurch characterized in that the respective one of the devices that have higher priorities than the respective device (e.g. N + 5) associated logic element, and that (e.g. B. 12-5) on the output side with an input which at the same time achieves an improved response time, associated locking device (16-5) via a further solution, the above-mentioned task is connected to logic element (14-5). which by the circuit characterized in claim 1 on the input side of the relevant display signal 40 arrangement. the associated device (N + 5) corresponding The invention is characterized by the advantage of a Signal can be fed. overall relatively low circuitry 3. Circuit arrangement according to claim da- wands. in order to achieve a versus the characterized in that the respective further previously known systems improved response time Linking element (14-3, 14-4, 14-5) through a 45 a priority-dependent release of in data transfer OR element is formed. institutions to be involved 4. A circuit arrangement according to one of the claims and not only that with regard to the priority before 1 to 3, characterized in that the locking devices of the respective device preceding devices (16-3, 16-4, 16-5) of all devices - direction to be taken into account, but in each case a provision (/ V + 3, Λ / + 4, N + 5) each with an inputted plurality of such devices, which went together at an output of a processing compared to the respective device with higher priorities processing device (10) are connected, of which have. said blocking signal can be emitted. Appropriate further developments of the invention result 5. Circuit arrangement according to one of the claims ben from the subclaims. before 1 to 4, characterized in that the mentioned 55 The invention is based on drawings a logic link (12-3, 12-4, 12-5) standing, for example, explained in more detail, of all devices (/ V + 3, Λ / + 4, Λ / + 5) each. Fig. 1 shows the connection of a plurality of uni an OR gate are formed. directions in a priority network. 6. Circuit arrangement according to one of claims F i g. 2 shows a further embodiment of the comparison 1 to 4, characterized in that the blocking 60 binding of a plurality of devices in one priority device (16-3, 16-4, 16-5) all device networks. lines (A / + 3, / V + 4, / V + 5) each by an AND Fig.3 shows a circuit arrangement according to the Link are formed. Invention for realizing what is indicated in FIG Priority network.