CH613061A5 - Computer apparatus including an omnibus line - Google Patents

Computer apparatus including an omnibus line

Info

Publication number
CH613061A5
CH613061A5 CH831676A CH831676A CH613061A5 CH 613061 A5 CH613061 A5 CH 613061A5 CH 831676 A CH831676 A CH 831676A CH 831676 A CH831676 A CH 831676A CH 613061 A5 CH613061 A5 CH 613061A5
Authority
CH
Switzerland
Prior art keywords
unit
units
priority
omnibus line
communication
Prior art date
Application number
CH831676A
Inventor
Frank V Cassarino Jr
George J Barlow
George J Bekampis
John W Conway
Richard A Lemay
David B O'keefe
Douglas L Riikonen
William E Woods
Original Assignee
Honeywell Inf Systems
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/591,964 external-priority patent/US3993981A/en
Priority claimed from US05/591,904 external-priority patent/US4000485A/en
Priority claimed from US05/591,902 external-priority patent/US4030075A/en
Application filed by Honeywell Inf Systems filed Critical Honeywell Inf Systems
Publication of CH613061A5 publication Critical patent/CH613061A5/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
    • G06F13/4213—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus with asynchronous protocol
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/378—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a parallel poll method

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)
  • Computer And Data Communications (AREA)

Abstract

It comprises several processing units, a priority allocation network (BSAUOK-BSIUOK, BSMYOK) to which each of these units is connected, and an omnibus line linking all the units in order to provide communication between any two of them. The apparatus is provided to enable each unit, concurrently with other units, to communicate with another via the omnibus line and at a speed depending on the sending unit itself and not on the limits imposed on all the communications. In order to determine, at any instant, which among several units simultaneously seeking to set up a communication, should have the priority, each unit comprises priority-determining circuits (Fig.) inserted into the said network according to a sequence which determines their relative priorities for the communications. Each circuit comprises means (15, 17, 18) for indicating that the unit in question requires communication with another unit, as well as means (19, 22, 23) allowing asynchronous transfer of information by this unit, via the omnibus line (10), when no unit having a higher priority is transmitting information nor is attempting to transmit it. <IMAGE>
CH831676A 1975-06-30 1976-06-29 Computer apparatus including an omnibus line CH613061A5 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US05/591,964 US3993981A (en) 1975-06-30 1975-06-30 Apparatus for processing data transfer requests in a data processing system
US05/591,904 US4000485A (en) 1975-06-30 1975-06-30 Data processing system providing locked operation of shared resources
US05/591,902 US4030075A (en) 1975-06-30 1975-06-30 Data processing system having distributed priority network

Publications (1)

Publication Number Publication Date
CH613061A5 true CH613061A5 (en) 1979-08-31

Family

ID=27416620

Family Applications (1)

Application Number Title Priority Date Filing Date
CH831676A CH613061A5 (en) 1975-06-30 1976-06-29 Computer apparatus including an omnibus line

Country Status (8)

Country Link
CH (1) CH613061A5 (en)
DE (1) DE2629401A1 (en)
FR (1) FR2316660A1 (en)
GB (1) GB1541276A (en)
HK (1) HK37180A (en)
NL (1) NL188920C (en)
SE (1) SE420360B (en)
SU (1) SU1274634A3 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4074353A (en) * 1976-05-24 1978-02-14 Honeywell Information Systems Inc. Trap mechanism for a data processing system
CA1120123A (en) * 1976-11-11 1982-03-16 Richard P. Kelly Automatic data steering and data formatting mechanism
ES474428A1 (en) * 1977-10-25 1979-04-16 Digital Equipment Corp A data processing system incorporating a bus
GB2076191B (en) * 1978-12-26 1983-06-02 Honeywell Inf Systems Improvements in or relating to terminal systems for data processors
FR2474199B1 (en) * 1980-01-21 1986-05-16 Bull Sa DEVICE FOR OVERLAPPING SUCCESSIVE PHASES OF INFORMATION TRANSFER BETWEEN SEVERAL UNITS OF AN INFORMATION PROCESSING SYSTEM
FR2474198B1 (en) * 1980-01-21 1986-05-16 Bull Sa DEVICE FOR DECENTRALIZING THE MANAGEMENT OF THE DATA TRANSFER BUS COMMON TO SEVERAL UNITS OF AN INFORMATION PROCESSING SYSTEM
IT1149252B (en) * 1980-09-09 1986-12-03 Sits Soc It Telecom Siemens INPUT-OUTPUT MODULE FOR AN ELECTRONIC PROCESSOR
US4724519A (en) * 1985-06-28 1988-02-09 Honeywell Information Systems Inc. Channel number priority assignment apparatus

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3815099A (en) * 1970-04-01 1974-06-04 Digital Equipment Corp Data processing system
US3676860A (en) * 1970-12-28 1972-07-11 Ibm Interactive tie-breaking system
US3832692A (en) * 1972-06-27 1974-08-27 Honeywell Inf Systems Priority network for devices coupled by a multi-line bus
US3866181A (en) * 1972-12-26 1975-02-11 Honeywell Inf Systems Interrupt sequencing control apparatus
US3886524A (en) * 1973-10-18 1975-05-27 Texas Instruments Inc Asynchronous communication bus

Also Published As

Publication number Publication date
FR2316660A1 (en) 1977-01-28
GB1541276A (en) 1979-02-28
DE2629401A1 (en) 1977-01-20
NL188920C (en) 1992-11-02
SE7607421L (en) 1976-12-31
SU1274634A3 (en) 1986-11-30
DE2629401C2 (en) 1989-01-19
SE420360B (en) 1981-09-28
NL7607167A (en) 1977-01-03
FR2316660B1 (en) 1983-05-13
HK37180A (en) 1980-07-18

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Legal Events

Date Code Title Description
PL Patent ceased