JPS5578561A - Master-slice lsi circuit device - Google Patents
Master-slice lsi circuit deviceInfo
- Publication number
- JPS5578561A JPS5578561A JP15097378A JP15097378A JPS5578561A JP S5578561 A JPS5578561 A JP S5578561A JP 15097378 A JP15097378 A JP 15097378A JP 15097378 A JP15097378 A JP 15097378A JP S5578561 A JPS5578561 A JP S5578561A
- Authority
- JP
- Japan
- Prior art keywords
- master
- memory
- region
- logic
- circuit group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 abstract 3
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
PURPOSE:To decrease delay in signal propagation by arranging a logic-gate circuit group and a memory-circuit group in respective regions in a master-slice LSI substrate in a coexistent-type architecture. CONSTITUTION:An LSI substrate 10 is divided into a region 11 where a logic-gate circuit group is constituted and a region 12 where a memory circuit group is constituted. This is a so-called logic-gate/memory coexistent-type master-slice substrate. A many number of logic gates 21 which constitute the region 11 are arranged in a scattered pattern of relatively low density for the sake of interlogic-gate wiring which will be laid out later. On the contrary, a many number of memory-circuit elements which constitute the region 12 can be formed as a master from the beginning since the wirings to be laid out later between individual memory circuits have a fixed pattern.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15097378A JPS5578561A (en) | 1978-12-08 | 1978-12-08 | Master-slice lsi circuit device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP15097378A JPS5578561A (en) | 1978-12-08 | 1978-12-08 | Master-slice lsi circuit device |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5578561A true JPS5578561A (en) | 1980-06-13 |
JPS6231501B2 JPS6231501B2 (en) | 1987-07-08 |
Family
ID=15508482
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP15097378A Granted JPS5578561A (en) | 1978-12-08 | 1978-12-08 | Master-slice lsi circuit device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5578561A (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57124463A (en) * | 1981-01-26 | 1982-08-03 | Nec Corp | Semiconductor device |
JPS5882533A (en) * | 1981-07-10 | 1983-05-18 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS61123154A (en) * | 1984-11-20 | 1986-06-11 | Fujitsu Ltd | Gate-array lsi device |
US4667310A (en) * | 1983-12-14 | 1987-05-19 | Kabushiki Kaisha Toshiba | Large scale circuit device containing simultaneously accessible memory cells |
US4675849A (en) * | 1982-07-26 | 1987-06-23 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5342578A (en) * | 1976-09-27 | 1978-04-18 | Siemens Ag | Semiconductor chip for producing lsi |
JPS53139284U (en) * | 1977-04-07 | 1978-11-04 | ||
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
-
1978
- 1978-12-08 JP JP15097378A patent/JPS5578561A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5342578A (en) * | 1976-09-27 | 1978-04-18 | Siemens Ag | Semiconductor chip for producing lsi |
JPS53139284U (en) * | 1977-04-07 | 1978-11-04 | ||
JPS53127285A (en) * | 1977-04-13 | 1978-11-07 | Mitsubishi Electric Corp | Semiconductor integrated circuit device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57124463A (en) * | 1981-01-26 | 1982-08-03 | Nec Corp | Semiconductor device |
JPS6262471B2 (en) * | 1981-01-26 | 1987-12-26 | Nippon Electric Co | |
JPS5882533A (en) * | 1981-07-10 | 1983-05-18 | Hitachi Ltd | Semiconductor integrated circuit device |
US4675849A (en) * | 1982-07-26 | 1987-06-23 | Tokyo Shibaura Denki Kabushiki Kaisha | Semiconductor device |
US4667310A (en) * | 1983-12-14 | 1987-05-19 | Kabushiki Kaisha Toshiba | Large scale circuit device containing simultaneously accessible memory cells |
JPS61123154A (en) * | 1984-11-20 | 1986-06-11 | Fujitsu Ltd | Gate-array lsi device |
Also Published As
Publication number | Publication date |
---|---|
JPS6231501B2 (en) | 1987-07-08 |
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