DE2033130A1 - Process for the production of a large-scale integrated circuit - Google Patents

Description

203313Q

Patent Attorneys Dlpl.-Ing. R, BEETZ sen. Dipl-lnc ·. K. LAIVPRIECHT

Dr.-Ing. Π. Π Ξ Π T Z jr. 8 Munich 22, Steinsdorfstr. 10

81-15.865P (15.866H) July 3, 1970

HITACHI, LTD., Tokyo (Japan),

Process for making an integrated

Capitalization

The invention relates to a method for producing a large integrated circuit, in particular a large integrated circuit, in which a plurality of λ

of unit cells on a semiconductor wafer mutually " get connected.

In particular, the invention relates to a wiring method, that when producing a large-scale semiconductor integrated circuit with a plurality of one another connected unit cells is applied.

As is known in the art, a large-scale semiconductor integrated circuit comprises numerous circuit elements, on a single semiconductor substrate

8i- (item 22 482) -Tp-r

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location are electrically combined to form an as Subsystem to result in working circuit. It includes actually several tens to several hundred times the number of circuit elements in the ordinary integrated Circuit that is abbreviated to "IC".

Usually when making an integrated Large-scale connection of a plurality of circuit elements to form a unit cell as an intermediate form with a specific one Circuit function united, and a plurality of such Unit cells are connected to one another in order to complete a desired large-scale layout, because it is the right one Arrangement of the individual circuit elements on a semiconductor substrate is facilitated »The leads or Wires for interconnecting these unit cells are formed by selectively connecting one first conductive metal layer deposited on an insulating layer that forms the main surface of the Semiconductor pad covered. There are also a second and further metallic conductive layers and insulating layers in between dejected to the wiring of the unit cells to manufacture. The wiring of the unit cells usually includes complicated patterns Crossing points. Accordingly, the first conductive layer in which the Unit cell surrounding part is provided and etched so that it forms an auxiliary conductor part of a pattern surrounding the individual unit cells. Usually the Auxiliary conductors in the step of forming leads shaped into a specific pattern around the internal wiring of the individual unit cells to be completed.

In the production of large integrated circuits

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it is extremely disadvantageous from the point of view of the production time and costs if all the necessary protective masks have to be designed individually for the various different possibilities of large switching dips. Therefore, one of the tasks in this field is to somehow design unit cells of roughly matching circuit shapes in order to make it possible to obtain different types of large-scale circuits from the same semiconductor wafer with a certain arrangement or distribution of unit cells by adding only those for the mutual wiring of the masks Λ used in the unit cells.

In the conventional method, however, the pattern is fixed for not only the unit cells but also the auxiliary conductor, so that the degree of freedom in designing the interconnection of the unit cells is low and there is a tendency; of the wiring leads is that they are rather crowded in the area surrounding the individual unit cells when the large-scale integrated circuit to be manufactured has a high degree of integration or a complicated circuit. Since the wiring is subject to serious restrictions, a desired large-scale integrated circuit cannot (J ^

can always be obtained without further ado.

It is therefore the object of the invention to provide an improved method for producing a large integrated circuit with a plurality of unit cells to indicate that it enables the mutual wiring of the unit cells to be simplified and a desired integrated one easily Large circuit with a high degree of integration.

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The object of the invention, with which this object is achieved, is a method for producing an inte-. integrated large-scale circuit with the characteristic) that a semiconductor wafer is produced, a plurality of unit cells spaced apart from one another and with electrodes on the surface of the semiconductor wafer, a conductive layer is attached at a distance around each unit cell, the conductive layer forming a more " * etches a number of narrow conductive layers, which covers narrow conductive layers with a thin insulating film, creates openings in the thin insulating film to expose the specific surface of the narrow conductive layer common to the desired unit cells and connecting lines of conductive layer between the electrodes of the desired unit cells and the openings for electrical purposes Connection of the desired unit cells via the connection lines and the narrow conductive layer attaches

According to the invention one can expediently an integrated Create a large-scale circuit by first producing the initial patterns that are used in the steps of formation individual unit cells are required on a semiconductor substrate, the unit cells on the semiconductor substrate with unitized large-scale circuit manufacturing masks, which are used at individual steps of the formation of the unit cells can be used by creating the initial pattern for each of the steps on the wafer surface to be masked in a repetition step or interval according to the degree of integration of the desired large circuit are arranged, the intermediate conductive layer being the individual Surrounding unit cells, one interconnection of the unit cells (the conductive layer is hereinafter referred to as the broad conductive layer) «« can be treated,

009883/1464

the remaining broad conductive layer surrounding the unit cells too narrow conductive layers after a suitable pattern for the mutual connection of the unit cells is etched is specified according to the particularities of the desired large circuit, and the unit cells with each other electrically connects via the narrow conductive layer.

Further it can be erfindungsgemäö produce a desired bulk circuit by forming a plurality of unit cells of a standard circle on a Halbleiterwaf- A fei, along an individual unit cells surrounding wafer surface portion provides a wide conductive layer, the connection leads to the individual unit cells for transferring a circuit eat other suitable Suitable for interrupting circuits by etching away the wide conductive layer to form narrow conductive layers in a required pattern and electrically connecting the unit cells converted into a circuit to one another via the narrow conductive strips.

According to the invention, on a semiconductor substrate Forming unit cell can not only be an integrated Circuit, but also a transistor, a diode or ||

other elements, such as B. an impurity diffusion resistance element or any combination thereof.

Furthermore, according to the invention, in the step of forming the wiring lead for the individual unit cells made of a 1 layer of conductive material deposited on an insulating layer that forms the Waffle surface covered with these unit cells, part of the low precipitation layer along the »Wafer surface area, which surrounds the individual unit cells,

0098SS / 1464

are left to form the broad conductive layer. Alternatively, the wide conductive layer can in other ways, such as B ₀ produced by the selective deposition method bodice _"o

Furthermore, the dimensions of the egg cells formed on the semiconductor wafer do not have to be constant, but rather some unit cells can be of larger dimensions compared to the. to be with others "The grid also snaps" the distance between the sinus cells is inconsistent

be constant, but can sometimes be bigger «special where some of the unit tariffs have a © complicated "circuit form , the space surrounding the unit cells of a complicated circuit is preferable bigger, because such a complicated. circuit with their Unit3! Cells probably have a complicated exterior Wiring required «

For the arrangement of the unit ropes on the semiconductor wafer in different individual positions, © riginalmuater can be manufactured in advance for a plurality of different types of unit cells as constituent elements of a plurality of large integrated derailleurs in - a reduced intermediate scale the desired large-scale circuits can be formed by means of a composition and repetition system. With these masks, air cells can be produced at different distances on the semiconductor wafer.

Bi © invention will orläitt aitharad the illustrated embodiments in the drawing in more detail © RTJ therein show ι

Fig. 1 to 3 partial views, partly broken away, to explain the process steps of an exemplary embodiment of the invention;

K and 5 are partial views for explaining a large number of unit cells which, according to the invention, are attached to a semiconductor wafer, FIG. 1 showing an inspection result of the unit cells;

^; -. ■ ■■■■ ..

Fig. 6 four identical, not interconnected ^p unit cells}

Fig. 7 is a circuit diagram of one by modifying and connecting circuit structure obtained from unit cells according to FIG. 6}

8 schematically shows a unit cell pattern in an intermediate process step for the production of a integrated large circuit according to the invention}

FIGS. 9 and 10 are schematic 'partial views of beispiels- λ have large circuit manufacturing masks according to the invention; and

11 is a schematic partial view of another for example large-scale circuit manufacturing mask according to the invention.

Embodiment 1

In FIG. 1, there is a semiconductor pad or wafer 1

Ö09886 / 14B4

«• ο -

with. Unit cells 7 to 10 shown o The semiconductor substrate 1 is Zo Bo 'a silicon monocrystalline waffle «On the main surface of the substrate 1, many circuit elements (not shown) are produced by means of a known selective impurity diffusion technique. These circuit elements are located within unit areas, as is typically indicated by a dashed rectangle 6 for the unit cell 7. They are protected by an insulating film 2, e.g. silicon dioxide film, which covers the main surface of the semiconductor substrate © 1- and the Circuit elements are interconnected by wiring lines 3 formed by selectively etching a first conductive metal layer deposited on the insulating film 2 to produce unit cells having particular circuit functions. In Fig. 1, the reference number h denotes the metal conductor connections of the unit cell®

The unit cell wiring lines 3 are formed by first making openings or windows at suitable locations in the insulating film 2 for necessary connection of the circuit elements, then making the insulating film 2 including windows with a conductive layer made of a conductive material such as aluminum, Nikkei, Molybdenum, chrome or gold covered either as a single layer or a combination of sublayers and then foiled to the conductive layer of the unit cell wiring to be weighed *

Afterwards, the conductive layer part 5 j © after the

special requirements of a desired integrated circuit large photo-etched to form narrow conductive strip 11 according to one adopted for the mutual wiring patterns, as shown in FIG. Z. The conductive layer 5 can also be used to form terminals common to the unit cells, such as, for. B. earth connection and power supply connection can be used. In this embodiment, a ground connection 12 is established which leads to all unit cells.

The narrow conductive strips thus formed on the semiconductor wafer are then covered with a thin insulating film 13 made of a material such as silicon dioxide, as shown in FIG. The insulating film 13 can be produced, for example, by thermal decomposition of monosilane in an oxygen atmosphere. Openings or windows are then made in the SiO ₂ film 13 where both the required locations of the narrow conductive strips 15 and the electrode parts of the unit cells are to be exposed. Then the insulating film 13 including the windows is covered with a second conductive layer Ik . Thus, the conductive layer 14 electrically connects the electrodes of the unit _{cells to the narrow strips 11 via the windows in the SiO 2} film.

In this way, the unit cells 7 to 10 are electrically connected via the connections ~ \ k and narrow conductive strips to form a desired large-scale integrated circuit.

In this embodiment, there is the narrow strip 11 by photo-etching the first conductive layer on the insulating layer in one of the desired type of grand-ch-aging appropriate patterns are formed, the mutual understanding

0 * 9866/1464

Wire casting of the unit cells less, restrictions in the The design of the wiring is subject to a Wiring disaster with bridging - to avoid Crossings applicable

Since one gnaw the pattern for the © conductive strips ,, from the first conductive layer are generated for the mutual wiring of the unit cells according to interpret the desired type of large-scale integrated circuit, it is according to the method according to the invention possible _t a selection of Manufacture large-scale circuit a from the semiconductor wafer ,, the unit cells of the same circuit structure contains ₉ so that a desired large-scale circuit is easily and inexpensively available "

Execution example 2

According to the invention, a desired large-scale integrated circuit can be formed from suitable unit cells selected from the unit cells on the wafer by measuring the electrical properties of the unit cells ₉ as shown in FIGS. 5 will be explained. In Fig. H , the reference number 15 denotes a silicon wafer on which a plurality of unit cells 16 are formed. The unit cells are produced according to a selective impurity diffusion technology. © rsseugio TataäehlicSa the arrangement according to Fig. 1 corresponds to an enlarged a. Part of the arrangement according to Fig. H “ Various ©! © ktrisetae Eigeras © stick to the so.

The units formed are measured to determine B ± ffl &®i-fescells;t> see it tiara tesa © lektiri

Find. Faulty © unit cells are indicated by a cross
marked in Fig. 5. This enables one to be selected
qualitative unit cell blocks that are used to manufacture
the integrated large circuit is suitable due to
the obtained distribution of qualified unit cells over the entire wafer surface. In Fig. 5 is a
Such a unit cell block is indicated by a dashed rectangle 20, while the reference number 18 denotes faulty unit cells and the reference number 19 denotes qualified unit cells.

After a suitable block has been selected, the same procedure as in embodiment 1 is carried out in the selected block in order to produce a desired large-scale integrated circuit; the wide conductive layer portion within the selected block is etched to narrow
To create conductive strips or layers according to a certain pattern, then the wafer surface containing the narrow conductive strips is covered with a thin insulating layer, windows or openings are then made in the thin insulating layer to expose certain parts of the narrow conductive strips, and finally a
conductive layer for electrical connection of the close / 4 conductive strip and the electrodes of the unit cells reasonable ^K

brought to complete the desired integrated large-scale circuit.

Embodiment 3

If, according to the invention, the unit cells of the structure with suitable intermediate internal connections in addition to the external connections and to change the unit cell

009886 / 148A

_ ₁₂ _ 203313Q

function depending on the requirements are suitable by if supply lines within the unit cell are appropriately interrupted, the same principle applies the step of making the internal wiring terminals as well as the production of the auxiliary conductive layer. Where the unit cells are suitable, their Modifying the circuit structure according to the design of the desired large-scale integrated circuit is one increased convertibility required for the mutual wiring of the unit cells with the auxiliary conductive layer is to be mastered. In this respect the technique according to the invention is extremely valuable.

An example of the creation of an integrated large scarf by modifying the circuit structure of unit cells “Shall now be described.

Fig. 6 shows an output arrangement. In this figure, four unit cells Zk to 27 are shown, each of which has two AND circles 21, an OR circuit 22 and a converter circuit 23. Thus, each unit cell has AND, OR and converter circuit functions. In fact, many such unit cells can be created in an array on a semiconductor wafer, although only four such unit cells are shown for ease of description and illustration. Among the four unit cells, the unit cell Zk is not subject to the partial removal of its inner terminals, while the other three "unit cells 25 to 2" are subject to the partial removal of their inner terminals to divide them into a plurality of parts, as shown in FIG shows »In detail, in the case of Einhelts cells 25 and 27, the wandering circle becomes

00S88S / 1464

separated from the rest of the circles, and at the unit cell 26 one of the AND gates is separated from the rest of the circles · In The strong lines 28 of the figure indicate the Unit cell interconnecting terminals, terminals 28 are actually the tight conductive strips that emerge from the wide conductive layer are formed, and they are, as before described, connected to a conductive layer, "

The output terminal of an AND gate which is present in the unit cell 26 and for which only the input terminal

I A3 is arranged to receive input current, is connected via H a line 29 to the output terminal of one of the AND gates contained in the unit cell 25 to form a triple-input AND gate, the AND output of which is the input terminal F of the OR gate of the unit cell 25, which in turn is connected in parallel to the OR gate in the unit cell 2k via lines 30 and 31 OR output in order to supply to the input terminal G of the transducer circuit of the unit cell Zh, I _n a similar manner connected to OR gate in the unit cell 27 through lines 32 and 33 parallel to the OR gate in the unit cell 26 · - to generate four inputs C to the input connections E, F-, E. and F.) an OR output for the purpose of feeding to the input connection G "of the converter relay of the binary cell 26. In fact, the input at the connection E" receives no input current, so that only the three Inputs (to the input connections F 1, E. and F j provide an OR output for feeding to the input connection Gw. Of the converter circuit of the unit cell 26.

Integrated circuit according to Fig. 7 has three Singangaansohlü ··· jk bl · 36, which have lines 28 «, 28«

009886 /

and 28 "are connected to corresponding AND gate connections, and two output connections 37 and 38" which are connected to an output connection X ₁ leading to the converter circuit of the unit cell Zk and to an output connection X "which is connected to the converter circuit of the unit cell 26 It functions as a binary adder receiving input signals Ai and Bi at the respective input terminals Jh and 35 and a carrier input signal Cn at input terminal J6 to produce an output signal ^ r ,,

Output terminal 37 and a carrier output signal

^C n ₊ 1 »< ^A i ^{+ B} iM ^C n ^{+ A} i

to be generated for the next stage at output terminal 38 "

During the actual production of the large-scale integrated circuit, the qualified unit cells are appropriately treated, some of which are their own supply lines Before removing the surface of the semiconductor wafer with an insulating layer of a material such as silicon dioxide is covered, followed by the step of attaching the wiring lines to connect the treated Unit cells follows.

In this embodiment it is possible to have many unit cells, e.g. B _e is shown in Fig .6, before to be placed on a semiconductor wafer and also to provide a wide conductive layer Läng d · ·· wafer surface part, the unglbt the individual unit cells ,, whereupon

0Ö988S / 1-4E4

203313Q

the electrical properties of the unit cells are measured, to check their qualifications, then select a block of qualified unit cells and afterwards the circuit conversion of the unit cells within the selected block and at the same time photo-etches the wide conductive layer into many narrow conductive strips, thereby the unit cells converted in terms of circuitry the narrow conductive strips are connected and an integrated Receive large switching with the desired behavior will.

Embodiment k

FIG. 8 shows a set of pattern masks which are required in both steps to combine many unit cells into a large-scale integrated circuit. Clear supports 39 »^ 0, 111, N have corresponding _{pattern zones A 1} , A„, · , Electrode openings and internal wiring of each unit cell are required. These unit cell patterns are prepared in advance for a plurality of basic circuits to give various types of large-scale integrated circuits. They can be produced preferentially by designing individual circuit elements and associated parts and copying them on a reduced scale from the master reticle »

In this exemplary embodiment, stockpiled ori-

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ginale for unit cell patterns for a plurality of different unit cells selected and appropriately combined according to the requirements of a desired large-scale integrated circuit "by employing a compounding and repeating system to create a large-scale circuit fabrication model mask where certain unit cell patterns are regularly graduated to a final scale" The repetition step or distance between adjacent unit cells can be varied according to the degree of integration of the large-scale circuit to be produced, which is a feature of this embodiment. For example, for a large-scale integrated circuit with a low degree of integration and a relatively small number of unit cells, individual unit cell patterns A can be arranged on a transparent base with a relatively narrow spacing d as shown in FIG relatively large number of unit lines the corresponding number of unit cell _{pattern A. can be arranged with a relatively wide spacing d g} according to FIG A, which are worked out on the basis of repeated attempts and checks, unit lines with certain properties can be obtained without errors.

When the unit cells are created in this way, a wide conductive layer to the surroundings of the individual unit cells for the purpose of mutual wiring of these unit cells in the manner described according to the first

QÖ9886 / H64

Embodiment made to achieve a desired inte * gri er te & r oß circuit asu received *

In this embodiment, the masks used in forming narrow conductive strips and unit cell terminals from the wide conductive layer may be hardwire meters designed for certain standard types of large-scale integrated circuits, or a selection of wiring patterns designed specifically for each semiconductor wafer term * Fe * tverdrahtungsmuster * is meant a wiring pattern \ is used when an integrated Großechaltung is created out of unit cells in certain mutual assignment · So the hard wiring patterns according to the invention, both in the process of attaching the wiring between unit cells on a semiconductor · " wafer independent of the qualification of the individual unit cells as well as suitable for the process of generating a large-scale integrated circuit with a 100 percent yield from only qualified unit cells, which in a special arrangement g focused on the semiconductor wafer oil and with the help of the inspection of each unit cell on which waffle are selected. With the ,-

Expression ! "Selection ^{wiring pattern 11} is a special-purpose * wiring buster designed for each wafer - as is known per se - by means of an electronic computer" according to the * distribution state of qualified cells on the semiconductor wafer.

In this »embodiment, since the stored original · for the unit cell pattern selectively according to the requirements of a desired in *, integrated large-scale layout can be used to

the large circuit creation mask under Arrange to generate unit cell patterns in gradations up to a final scale in one repeating step, which is determined by the degree of integration of the desired large-scale circuit, reducing the time required to produce a large-scale circuit manufacturing mask, and • There is also a large integrated circuit available without overly crowded wiring connections between the unit cells.

Can also be in this embodiment, if the unit cells of the structure with suitable intermediate internal connections in addition to the external connections and are suitable for converting the unit cell function by appropriate interruption of the lines within the unit cells, as in embodiment 3 the use the same pattern mask in the step of making the internal wiring connections and in the step of forming the auxiliary conductive layer expand.

/ Waiter it is, though in the previous examples

™ the unit cell pattern of the same type is arranged on a mask base at a constant repetition distance are also possible according to the invention to arrange two or more different types of binary cell names on a mask base, which consist of a plurality of front, different cling cell amsterite manufactured in suitable repetition steps are selected.

For example, FIG. Tt sweier an arrangement of various kinds of EinheitsaeileniBtaaterK B ^ wind B ₂

§0983671414

At absent intervals d ", d. and d., Venn the in Flg. 11 is used to produce a large integrated circuit in the same way as in the previous examples. Integrated large-scale circuits can become more complicated Circuit functions in comparison old the previous examples games in which the same unit cell patterns are arranged in constant repetition step, easily make,

■■■ '.'. ": ■■ A.

By widening the conductive layer part by a unit cell with a particularly complicated circuit structure in comparison with the part by unit cells of simpler circuit types, the production of the overall circuit can be facilitated and the yield can be increased.

Also do not need the dimensions of the unit cells to be even, but you can also use unit rope accommodate larger dimensions

Veiter 1st this embodiment, even when manufacturing a large-scale integrated circuit according to the so-called 'th "Selektivverdrahtungsmueterverfahren * applicable where the Einheitβzellen formed on a semiconductor wafer is measured with respect to their electrical properties, and only qualified unit cells are wired together to form the Großachaltung. The effect of the extended versatility the pattern design is very large.

As shown in the foregoing, according to the present invention, the unit cells are used in the large-scale integrated circuit

009886 / U64

UJo! Ου

each wired through many narrow conductive strips, which are attached to the unit cells ₅ so that the compared = "side wiring is simple and extremely avoids the crossing of Verdrahtungsleittingen." So the yield is very much increased

Is also as the unit Sell patterns for a plurality of different unit lines earlier prepared z _ä B ₀ in a reduced Zwisehenmaßstafo and are selectively used to generate a large circuit manufacturing pattern mask after the Abstuf- and ¥ iederholsy © system in accordance with the requirements of the desired bulk circuit, the time required for the production of the large-scale circuit production mask is greatly reduced. Furthermore, since the repetition distance in the step of generating the large-scale circuit can be varied according to the degree of integration of the large-scale circuit, there is a sufficient area for the mutual wiring of the unit cells of an integrated large-scale circuit A high degree of integration available «In addition, the pattern for the mutual wiring of the unit cells can be greatly simplified.

009886/1464

Claims (1)

Claims .7A method for producing an integrated large formwork, characterized in that a semiconductor wafer is produced, a plurality of unit cells spaced apart from one another and with electrodes formed on the surface of the semiconductor wafer, a conductive layer spaced around each unit cell, the conductive layer being formed one more « (m number of narrow conductive layers etches, the narrow conductive layers with Ί covered with a thin insulating film, openings in the thin insulating film to expose the particular, desired din Unit cells common surface of the * narrow conductive layer creates and connecting lines of conductive layer between the electrodes of the desired unit cells and the openings for the purpose of electrical connection of the desired Attaching unit cells over the connecting lines and the narrow conductive layer. 2. The method according to claim 1, characterized in that that between the formation of the conductive layer and the Etching the conductive layer the electrical properties * each unit cell for the purpose of selecting unit cells of desired electrical properties from the total number of the available unit cells and selects the block of the desired shape on the wafer in which the selected unit cells with the desired electrical properties are included, and that the etching of the conductive layer and the further process steps only performs in this block 3 · Method according to claim 1 or 2, characterized in that 003886/1464 indicates that when the unit cells are formed, the standard " unit cells are formed. k. Method according to claim J ₉ characterized by » net that one continues to etch some of the standard unit cells, another desired © circuit resin parts » 5. The method according to claim 1 or 2 " characterized in that when the unit cells are formed, the unit cells are distributed in such a way that the distance between certain restraint ropes is different from that between other unit cells. 6. The method according to claim 5 »characterized in that when etching the conductive layer, this is etched so that many narrow conductive © layers in the part with a large distance between the units and a few en ^ e conductive layers in the part with a small distance between the unit cells are generated » 7. The method according to claim 1, characterized in that that when the unit cells are formed, each dimension of the unit cells is made different from one another " 8. Method according to claim 2, characterized in that that in forming a plurality of unit cells at least a unit cell of large ones. Dimensions forms. 9. The method according to claim 1, characterized in that that among the initially formed units only very few « a "unit cell with a complicated circuit, 00-9888 / 1464 the distance between the unit cell of complicated circuit and neighboring other unit cells larger than that is between the other unit cells * and that the Number of narrow conductive layers around this complex circuit unit cell is greater than that of narrow conductive layers Layers around the other unit cells 1st