ES438666A1 - Integrated circuit structure - Google Patents
Integrated circuit structureInfo
- Publication number
- ES438666A1 ES438666A1 ES438666A ES438666A ES438666A1 ES 438666 A1 ES438666 A1 ES 438666A1 ES 438666 A ES438666 A ES 438666A ES 438666 A ES438666 A ES 438666A ES 438666 A1 ES438666 A1 ES 438666A1
- Authority
- ES
- Spain
- Prior art keywords
- cells
- lines
- resistors
- transistors
- groups
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
- H01L27/11801—Masterslice integrated circuits using bipolar technology
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
Improvements introduced in a semiconductor chip structure of integrated circuits in a plane, a structure that comprises a surface from which a plurality of regions of different types of conductivity extend that enter the chip forming transistors and resistors, the improvement in which said transistors and resistors are arranged in a plurality of repetitive cells, each of said cells containing a sufficient number of transistors and resistors to form a chosen type of logic circuit, and said cells being arranged in an orthogonal formation, with cells in essentially parallel rows in both orthogonal directions; and in which the structure includes a metallization level arranged above said formation and isolated from it by at least one layer of electrically insulating material, said metallization level comprising a plurality of groups of essentially parallel lines, respectively arranged above of and parallel to a corresponding plurality of interfacial zones or transition faces between rows of said cells in one of said orthogonal directions, each group of lines being connected to a plurality of cells that apply to the transition face below said group, providing interconnections between said cells, and voltage level supplies for them, and distribution designs or guidelines of lines respectively arranged between said groups of lines and at a certain separation distance from them and above said cells, providing intracellular connections. (Machine-translation by Google Translate, not legally binding)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US48346374A | 1974-06-26 | 1974-06-26 |
Publications (1)
Publication Number | Publication Date |
---|---|
ES438666A1 true ES438666A1 (en) | 1977-03-16 |
Family
ID=23920133
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES438666A Expired ES438666A1 (en) | 1974-06-26 | 1975-06-18 | Integrated circuit structure |
Country Status (8)
Country | Link |
---|---|
JP (2) | JPS5125085A (en) |
CA (1) | CA1024661A (en) |
CH (1) | CH583970A5 (en) |
DE (1) | DE2523221A1 (en) |
ES (1) | ES438666A1 (en) |
FR (1) | FR2276693A1 (en) |
GB (1) | GB1513893A (en) |
IT (1) | IT1038108B (en) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL185431C (en) * | 1977-05-31 | 1990-04-02 | Fujitsu Ltd | INTEGRATED SEMICONDUCTOR CIRCUIT, INCLUDING A SEMICONDUCTOR BODY WITH AT LEAST TWO BASIC CIRCUITS OF COMPLEMENTARY FIELD EFFECT TRANSISTORS WITH INSULATED CONTROL ELECTRODE. |
CA1102009A (en) * | 1977-09-06 | 1981-05-26 | Algirdas J. Gruodis | Integrated circuit layout utilizing separated active circuit and wiring regions |
DE2822011B2 (en) * | 1978-05-19 | 1980-06-04 | Fujitsu Ltd., Kawasaki, Kanagawa (Japan) | Semiconductor device and method for the production thereof |
US4249193A (en) * | 1978-05-25 | 1981-02-03 | International Business Machines Corporation | LSI Semiconductor device and fabrication thereof |
FR2443185A1 (en) * | 1978-11-30 | 1980-06-27 | Ibm | TOPOLOGY OF INTEGRATED SEMICONDUCTOR CIRCUITS AND METHOD FOR OBTAINING THIS TOPOLOGY |
JPS5712534A (en) * | 1980-06-27 | 1982-01-22 | Hitachi Ltd | Semiconductor device |
FR2495834A1 (en) * | 1980-12-05 | 1982-06-11 | Cii Honeywell Bull | INTEGRATED CIRCUIT DEVICE OF HIGH DENSITY |
JPS57186350A (en) * | 1981-05-13 | 1982-11-16 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS58112343A (en) * | 1981-12-26 | 1983-07-04 | Olympus Optical Co Ltd | Semiconductor and manufacture thereof |
JPS58143550A (en) * | 1982-02-22 | 1983-08-26 | Nec Corp | Semiconductor device |
JPS5943548A (en) * | 1982-09-06 | 1984-03-10 | Hitachi Ltd | Semiconductor integrated circuit device |
JPS59103455U (en) * | 1982-12-28 | 1984-07-12 | 富士通株式会社 | semiconductor equipment |
EP0113828B1 (en) * | 1983-01-12 | 1990-02-28 | International Business Machines Corporation | Master slice semiconductor chip having a new multi-function fet cell |
JPS59159558A (en) * | 1983-03-01 | 1984-09-10 | Toshiba Corp | Semiconductor substrate |
JPS63278249A (en) * | 1986-12-26 | 1988-11-15 | Toshiba Corp | Wiring of semiconductor integrated circuit device |
EP0387812A3 (en) * | 1989-03-14 | 1992-08-05 | Fujitsu Limited | Bipolar integrated circuit having a unit block structure |
DE10317018A1 (en) * | 2003-04-11 | 2004-11-18 | Infineon Technologies Ag | Multichip module with several semiconductor chips and printed circuit board with several components |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR1064185A (en) * | 1967-05-23 | 1954-05-11 | Philips Nv | Method of manufacturing an electrode system |
DE1789137A1 (en) * | 1967-06-23 | 1973-05-03 | Rca Corp | CIRCUIT CONSTRUCTED FROM UNIT CELLS |
US3558992A (en) * | 1968-06-17 | 1971-01-26 | Rca Corp | Integrated circuit having bonding pads over unused active area components |
US3584269A (en) * | 1968-10-11 | 1971-06-08 | Ibm | Diffused equal impedance interconnections for integrated circuits |
US3656028A (en) * | 1969-05-12 | 1972-04-11 | Ibm | Construction of monolithic chip and method of distributing power therein for individual electronic devices constructed thereon |
US3621562A (en) * | 1970-04-29 | 1971-11-23 | Sylvania Electric Prod | Method of manufacturing integrated circuit arrays |
US3771217A (en) * | 1971-04-16 | 1973-11-13 | Texas Instruments Inc | Integrated circuit arrays utilizing discretionary wiring and method of fabricating same |
US3725743A (en) * | 1971-05-19 | 1973-04-03 | Hitachi Ltd | Multilayer wiring structure |
US3808475A (en) * | 1972-07-10 | 1974-04-30 | Amdahl Corp | Lsi chip construction and method |
-
1975
- 1975-04-22 CA CA225,413A patent/CA1024661A/en not_active Expired
- 1975-05-13 IT IT2325375A patent/IT1038108B/en active
- 1975-05-21 FR FR7516533A patent/FR2276693A1/en active Granted
- 1975-05-21 GB GB2187575A patent/GB1513893A/en not_active Expired
- 1975-05-26 DE DE19752523221 patent/DE2523221A1/en active Granted
- 1975-06-04 JP JP6665775A patent/JPS5125085A/en active Granted
- 1975-06-16 CH CH775675A patent/CH583970A5/xx not_active IP Right Cessation
- 1975-06-18 ES ES438666A patent/ES438666A1/en not_active Expired
-
1983
- 1983-10-20 JP JP19540983A patent/JPS5989435A/en active Pending
Also Published As
Publication number | Publication date |
---|---|
FR2276693A1 (en) | 1976-01-23 |
JPS5753984B2 (en) | 1982-11-16 |
DE2523221C2 (en) | 1992-09-17 |
DE2523221A1 (en) | 1976-01-15 |
CA1024661A (en) | 1978-01-17 |
JPS5125085A (en) | 1976-03-01 |
IT1038108B (en) | 1979-11-20 |
FR2276693B1 (en) | 1977-04-15 |
CH583970A5 (en) | 1977-01-14 |
JPS5989435A (en) | 1984-05-23 |
GB1513893A (en) | 1978-06-14 |
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