JPS6298641A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the generation of electro migration in the aluminum wirings without spreading the wiring width of the signal lines by a method wherein the functional block is provided with a plurality of pieces of equivalent output terminals connected with a metal wiring. CONSTITUTION:This layout pattern is ready-changed in such a way that several equivalent output terminals can be secured. That is, equivalent output terminals 31A and 31B are directly connected with an Al wiring 30 and can be used as the equivalent output terminals, and contacts 31A and 31B can be used according to an operating frequency and a load capacity. For example, in the case the load capacity is large, a through hole 32A is put on a lattice in the vicinity of the output terminal 31A, the 31A and the 32A are connected with a first layer Al wiring to wire a second layer Al wiring 33A from the through hole 32A in a Y direction and moreover, a first layer wiring 35A is wired in a through hole 34A and the terminal 31A is connected to an input terminal of other functional block, and at the same time, the terminal 31B is also connected to an input terminal of other functional block in the same shape as the above. By splitting the load capacity in such a way, the current density of the wiring from each output terminal can be reduced.

Description

[Detailed Description of the Invention] [Industrial Application] The invention is directed to a CMOS master slice type integrated circuit or a standard cell type integrated circuit, which is arranged on a gate basic cell used in an internal area. Regarding functional blocks.

[Conventional technology]

As an example of this kind of conventional functional implementation, FIG. 2 shows the layout of an LC CM OS inverter circuit using two gate basic cells. In FIG. 2, one gate basic cell 1 has a P-channel transistor region 2 with V in the X direction. A polysilicate gate 4 is provided in the X direction along which the oWL source line 3 traces, and has a source region 5 and a drain region 6, and the N channel transistor region 12 is connected to the X direction GND.
A power supply line 13 passes through it, an X-direction polysilicate gate 14 is provided, and it has a source region 15 and a drain region 16 .

Further, in FIG. 2, marks X indicate contacts, and marks 0 indicate through holes connecting the first layer of aluminum and the second layer of aluminum. As shown in the figure, a CMOS inverter circuit is constructed by connecting predetermined contacts using aluminum wires 7 and 8. A contact 21 is generally defined as its output terminal.・The wiring from this side is automatically done using a CAD system. Draw all the through holes 22 in the vicinity of the normal contacts 21, and from here draw the wiring 23 in the Y direction using the second layer aluminum wiring, and then connect the through holes. ; Wiring 25 is drawn in the X direction every 24 minutes. In this way, the first layer aluminum wiring, the second layer aluminum wiring, through holes, and contacts are used to connect to the input terminals of a plurality of functional blocks in the next stage.

[Problem that the invention seeks to solve]

In the conventional functional blocks mentioned above, the channel grid is defined so that automatic wiring can be performed, so the wiring width is uniquely determined by the aluminum wiring, and you can freely make it thinner or thinner.
I can't get it to be thick enough. Therefore, for example, the above-mentioned CMOS
The switching frequency of the inverter circuit increases, and the current flowing through the signal line becomes proportional to the switching frequency.
Moreover, it cannot cope with the increase in load capacitance attached to the signal line in proportion to zero. Furthermore, the current flowing through the signal line changes depending on the ON resistance (1) of the inverter circuit. Under these circumstances, if the load capacity is large (specifically, the number of fan-outs (Flo) is large and the length of the aluminum wiring is long) and the operation is performed at high speed, the current flowing through the signal line will naturally increase. If the value is large, there is a risk that electromigration will occur in the aluminum wiring, so the load capacity and switching frequency will be limited.

[Means for solving problems]

In the semiconductor integrated circuit of the present invention, a plurality of gate basic cells are arrayed on a semiconductor chip, and a wiring region defining a wiring channel lattice is provided between the gate basic cells.
By connecting the gate basic cells along the wiring channel lattice, in a semiconductor integrated circuit constituting a logic circuit, functional blocks arranged on the gate basic cells can be connected to equivalent output terminals by metal wiring. It is characterized by having multiple.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a layout diagram of functional blocks of a simple embodiment of the present invention. Parts common to FIG. 2 are indicated by the same numbers and symbols. The difference from the conventional example shown in Fig. 2 is that the layout pattern has been changed so that several equivalent output terminals can be installed, and the equivalent output terminals 31A and 31B are directly connected with aluminum wiring 30. It is a point.

By doing so, the contacts 31A and 31B can be used as equivalent output terminals depending on the operating frequency and load capacity. For example, if the load capacity % is large, make a note of a through hole 32A in the grid near the output terminal 31A, connect 31A and 32A with the first layer aluminum wiring, and wire the second layer aluminum wiring 33A in the Y direction from the through hole 32A. 1. Also, in the through hole 34A, the first layer wiring 35A
The terminal 31B is wired and connected to the input terminal of another functional block, and the terminal 31B is also connected to the input terminal of another functional block in a similar manner. By making the negative iπ capacitance polluted in this way, the wiring from each output terminal is
The a-flow rate can be reduced.

〔Effect of the invention〕

As explained above (・ζThe present invention allows the functional block to have a plurality of equivalent output terminals connected by metal wiring, so that when the functional block operates at high speed and has a large load capacitance, the equivalent output terminal By separating the output signal lines by using a It has the effect of preventing injury from occurring.

[Brief explanation of drawings]

FIG. 1 is a functional block layout diagram of a semiconductor integrated circuit according to the present invention, and FIG. 2 is a conventional functional block layout diagram. Agent Patent Attorney r3. ″1, i 26B Mu7 Fujo 2 Ward

Claims (1)

[Claims] By arranging a plurality of basic gate cells on a semiconductor chip, providing a wiring area defining a wiring channel between the basic gate cells, and connecting the arranged basic gate cells along the wiring channel lattice. A semiconductor integrated circuit constituting a logic circuit, characterized in that a functional block arranged on a basic gate cell has a plurality of equivalent output terminals connected by metal wiring.