JPS60115241A - Logic cell for lsi device and lsi device using - Google Patents

Abstract

PURPOSE:To facilitate an automatic layout using a computer without complicating the algorithm of arrangement and wiring, by using a logic cell designed so that it can prevent cell symbol informations required for automatic arrangement and wiring from being affected by a gate size. CONSTITUTION:An inverter cell A is constructed of a gate wiring region 81, a diffused layer region 82 and a wiring region 83, and an MOS transistor is formed in a region surrounded by L and W1, while a gate size is determined as W1/L. In an inverter cell B, the width W2 of a diffused layer region 82 is narrower and a gate size W2/L is smaller than in the cell A. The respective distance of these cells from the position 24 of the origin and the width thereof are fixed so that power supply lines 25 and 26 are connected together when the cells are juxtaposed laterally, and the respective height H of the cells is determined so that they can be laid out both for the maximum and minimum values of a gate width, whereby the position of a power source is fixed. The positions 22 and 23 of input/ouput terminals are set in the same place, since the logical constructions of the cells are identical. Thus, the cell symbol figures C of the two cells A and B different in the gate width from each other are made to be identical.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a logic cell for an LSi device and an LSi device using the LSi device.
Regarding SI devices, especially automatic placement and
[Background of the Invention] Conventionally, as a method for layerer 1 of a logic LSI device, NΔ
1) Prepare a pre-layout pattern for each logic unit such as ND, NOR, etc. as a standard logic cell, and arrange the standard logic cells and wire between the cells to create a layout of a complex and large-scale LSI device. A method of doing this is used. Further, automatic layout using a computer stores the symbols of the standard logic cells and automatically performs the arrangement and wiring processing according to a certain algorithm under the evaluation condition of minimizing the overall area, for example. is also being carried out.

Incidentally, the amount of current flowing through the MOS devices constituting the logic LSI device is proportional to the device size, that is, the ratio of channel length to channel width W, W/L. The operating speed of the gate is determined by the speed at which the output capacitance of the gate is charged and discharged by the current flowing through the gate. Further, the output capacitance is determined by the number of gates in the next stage connected to the gate and the wiring length to the gate. That is, as the number of gates (fan-out) in the next stage increases and as the wiring length increases, the load capacitance increases and the operation speed of the gate decreases. FIGS. 1 and 2 illustrate the above-mentioned relationship using a CMOS gate as an example.

In the design of LSI devices, the operating speed Tp of game 1-
A method is adopted in which the gate size W/L is made as small as possible within a range where d satisfies the design target to lower the peak current. This is because when a large number of gates connected to a power line operate simultaneously, a current equal to the sum of the peak currents of all gates flows through the power line, causing a voltage drop due to the wiring resistance of the power line, which causes the power supply voltage to This is to try to minimize as much as possible the causes of fluctuations. Furthermore, in the case of aluminum wiring, it may cause electromigration.

By the way, when using the layout method using automatic wiring, the arrangement and wiring of cells are automatically determined, so it is not possible to estimate the load capacitance due to the wiring length in advance. For this reason, when using cell needles with small W/L, if placement and wiring are done in such a way that the wiring length becomes long,
There is a risk that the operating speed intended when designing the cell may not be achieved.

In order to prevent this, conventionally, a cell having a W/L that satisfies the operating speed with respect to the load capacitance under this condition has been used, assuming the longest wiring length that occurs in the automatic membrane n1. However, with this method, the peak current per gate inevitably increases, and in ultra-highly integrated LSI devices using microprocesses, the characteristics deteriorate due to fluctuations in the power supply voltage and migration described above, and sufficient LSI is required.
There was a problem that it became difficult to achieve the SI device performance.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and its purpose is to solve the above-mentioned problems in conventional automatic design, and to complicate placement and wiring algorithms for automatic layout using computers. It is an object of the present invention to provide a logic cell for an LSI device having a structure suitable for optimizing gate operation speed, and an LSI device using the logic cell.

[Summary of the invention]

The key point of the present invention is that in conventional logic cells, when the logic configuration is the same but the gate size W/L is different, the cell symbol information such as the cell size and signal terminal position is designed to be different. Cell symbols within a certain range of gate size W/L are now defined for each logic configuration, and the cell symbol information required for automatic placement and routing is not affected by gate size W/L. When automatic placement and wiring are performed, the gate size W is determined according to the load capacitance determined by the layout result.
Even if /L is changed, the cell symbol information required for automatic layerer 1~ will not change at all, and even if automatic placement/routing processing is performed again, only the gate size W/L in the changed cell will change. The point is that no change occurs in the cell arrangement or wiring state.

[Embodiments of the invention]

Hereinafter, embodiments of the present invention will be explained in detail based on the drawings.

3(A) to 3(C) show an embodiment of the present invention, FIGS. 3(A) and 3(B) are diagrams showing the structure of the inno It is a symbol diagram.

In FIG. 3(A), 81 is the goo 1 to wiring area, 82
Reference numeral 83 indicates a diffusion layer region, numeral 83 indicates a wiring region, and numeral 84 indicates a contact for connecting the regions 82 and 83. In addition, in this figure, PMO8 and NMO
The well formation pattern forming region 8 is omitted. The Mos transistor is formed in the region surrounded by L and W in the above figure, and the gate size is W, /l.6 Figure 3 (B) also shows an inverter cell; The difference from the cell shown in (A) is that the diffusion layer region 8
The point is that the width of 2 is as narrow as wt.

The gate size is W, /L, as shown in Figure 3 (A) □
It's smaller than what I did.

FIG. 3(C) is a symbol diagram common to the above (A) and (B), where 21 is a cell boundary, 22 is a gate input position, and 23 is a symbol diagram common to (A) and (B).
24 indicates the gate output position, 24 the origin of the cell, 25 the Vcc terminal, and 26 the Vss terminal. The cells are arranged at a constant distance and width from the origin position 24 so that the power lines 25 and 26 can be connected by arranging them side by side.

Since the power supply wiring generally uses a metal layer and can be placed over the diffusion layer, the height H of the cell that can be laid out for both the maximum and minimum gate widths is determined. Fix the power position. Figure 3 (A),
As shown in (B), the diffusion layer 82 and the metal wiring layer 83 can be overlapped, and when W is small, the shape becomes complicated due to the area required to maintain contact between the eyebrows. For this reason, there is almost no difference in height (T) caused by a difference in gate width, and there is almost no increase in cell area.

Since the input/output terminal positions have the same logical configuration, there is no particular problem in arranging the input/output terminals at the same positions. Originally, the origin position has the property of being able to be set at any arbitrary position. Two cells with different gate widths made in this way are shown in Figure 3 (A
), the cell symbol diagram (C) of the cell shown in (B) will be exactly the same.

For placement and wiring layout in units of cells, specify the correspondence between each logic circuit and the aforementioned cells from the logic drawing,
As mentioned above, when these cells are automatically laid out by a computer by wiring them according to the connection information in the logic diagram, the cell placement and wiring are done according to some kind of algorithm that optimizes the evaluation index. .

A relatively commonly used evaluation index is one that minimizes the area to be laid out.

The simpler the evaluation index is, the shorter the computer processing time will be, so it is not preferable from the point of view of design efficiency to use an evaluation index that includes the operating characteristics of the LSI device. In the case of a layout that is automatically placed and wired based on an evaluation index that does not include the operating characteristics of the LSI device, as described above, there is a possibility that gates may not be able to reach a predetermined operating speed depending on the length of the wiring. however.

By using the cell shown in this example, even when automatic placement and routing is performed using an evaluation index that does not include the operating characteristics of the LSI device, a layout that optimizes performance and minimizes peak current can be created. realizable. This will be explained in detail below.

FIG. 4 shows a part of the logic circuit. In this circuit, IIA and IIB are inverters, 12A, 12B
is a 2-man powered NAND gate, 13 is a 3-man powered NAND-gate, 14A and 14B are 2-man powered NOR gates, 15 is FO
This is the R gate. FIG. 5 shows the results of forming each logic gate into cells, arranging and wiring them, and performing step A. FIG. 5 shows three rows of cells. By arranging each cell column with the origin on the same horizontal axis.

The power supply line is connected between each cell as shown in 31.32. Cells that are not particularly numbered and explained in FIG. 5 are cells that correspond to logic circuits other than those shown in FIG. 4.

Cases in which automatic placement and wiring are performed using an evaluation index such as minimizing the area 1 For example, layerers with extremely different gate loads, such as inverters IIA and IIB,
There may be consequences. Even in such a case, the layout is performed using the following procedure in order to optimize the circuit characteristics.

That is, first, the layout pattern of FIG. 5 is generated for the logic circuit of FIG. 4 using a cell with the smallest gate size W/L as shown in FIG. 3(B). When a cell with the minimum W'/L is used, the peak current flowing through the cell is minimized, as shown in FIG.

Next, the load capacitance is calculated from the obtained shearout pattern of FIG. 5, and it is evaluated whether the target circuit performance is satisfied.

For example, as in the inverter ILB in Fig. 5, the wiring length <(
21B) Cells with large load capacity are automatically placed/placed again by matching cells with large W/L as shown in Figure 3 (B).
Perform wiring. At this time, since the cells shown in FIGS. 3A and 3B have the same boundary conditions, that is, the shape of the cell, the position of the signal end, the position of the power supply, the origin, etc., the arrangement after processing The wiring result is exactly the same as shown in FIG. However, in the above inverter IIB, as shown in FIG. 3(A),
The cell shown in FIG. 3(B) corresponds to the inverter 11A, and the layout pattern within the cell is different.

Determining the load capacitance of the gate from the above-mentioned placement/wiring results and determining a cell according to the circuit performance can be performed completely independently of the automatic placement/wiring.

Therefore, there is no need to change (complicate) the automatic placement/routing algorithm in any way.

Although the case where the logic gate and the cell with the minimum W/L are first associated is described here, the cell with the maximum W/L may be associated first. The placement and wiring results that have been automatically wired will not change as long as the W/L is changed within a range that fits within a common cell. Therefore, if the '7'-1- cell correspondence is optimized by load analysis of the layout result, it does not matter which WZL size is used initially.

In the above embodiment, the cell symbol corresponds to one simple gate, but by taking exactly the same correspondence to flip-flops, registers, ALUs (arithmetic circuits), etc. that are composed of multiple gates, this invention can be applied. The Layer 1 method shown in the example can be adopted.

As shown in FIGS. 3(A) and (B), the cell symbol can be divided into the range of gate size W/L appropriately, and by internally changing the layout pattern, the same cell symbol size can be changed to W. /L different layouts can be formed without waste.

In Figure 3, the width of the cell is determined by the aluminum line width, and the diffusion layer forming the gate is multilayered with this aluminum layer.
The cell size is the same whether the gate width is wl or wl.

In the future, the process for forming LSI devices will move toward multilayering, and it is thought that it will become easier in the future to change the gate size W/L while keeping the size of the cell symbol constant.

〔Effect of the invention〕

As described above, according to the present invention, the gate size W/L
We have defined cell symbols within a certain range for each logic configuration so that the cell symbol information required for automatic placement and routing is not affected by gate size W/L, so it is possible to use cell symbols without considering load conditions. This has the remarkable effect of making it possible to layout LSI devices and facilitating mechanical layout such as automatic layout using a computer. In addition, you can optimize the size of goo 1 after laying out each cell symbol,
There is also the effect that optimal conditions can be determined by l-tube down design.

[Brief explanation of the drawing]

Figure 1 shows gate size W/L and gate delay time Tpd.
Graph showing the relationship between the gate current and the peak current of the gate, the second
The figure is a graph showing the relationship between wiring length and load capacity.
A) and (B) are cell configuration diagrams showing one embodiment of the present invention, (C) is a symbol diagram thereof, No. 4 @ is a diagram showing an example of a logic circuit, and FIG. 5 is a cell diagram for the above logic circuit. FIG. 3 is a diagram showing the arrangement/wiring layout used. 11A, IIB: Inverter, 12A, 12B:
2-man power NAND gate, 13:3 man-power NAND gate, 14A. 14B: 2-man power NOR gate, 15: EOR gate, 21: Cell boundary, 22: Input terminal, 23: Output terminal, 24: Origin, -25, 26: Power supply terminal, 81 Nige-1
- Wiring region, 82: Diffusion layer region, 83: Wiring region, 84
:contact.

Claims (2)

[Claims] (1) Perform cell layerer 1- within a certain rectangular area for logic circuits with the same logic configuration and number of inputs and outputs, and place terminals corresponding to the inputs and outputs within the rectangular area or at fixed positions on the boundaries. It is characterized in that it is configured so that the channel width or channel length of the gate can be changed within the rectangular region. Logic cells for LSI devices. (2) For logic circuits with the same logic configuration and the same number of inputs and outputs, perform cell layerer 1 within a certain rectangular area and provide terminals corresponding to the inputs and outputs within the rectangular area or at fixed positions on the boundaries. At the same time, the placement and wiring layout between two or more logic groups 1 to 1 is performed using logic cells configured to change the channel width or channel length of the gate within the rectangular area, and if necessary, the layout results are LS characterized in that it is constructed by replacing a logic cell within the LS with another logic cell of the same logic configuration and size having a different channel width or channel length.
I device.