JPS58197747A - Master slice lsi - Google Patents

Abstract

PURPOSE:To reduce the number of pieces of no wiring of automated wirings at the center part of a chip by a method wherein no cell arranged regions are provided on the lines of circuit elements at the center part of the chip, and wirings to connect between cells are provided thereto crossing at a right angle to the lines of the circuit elements. CONSTITUTION:The desired cells 3 are arranged on the chip 1, and the cells 3 thereof are connected with straight lines 9. At this time, when the places to make the straight lines 9 thereof to cut the cells 3 vertically are made as the no cell arranged regions, arrangement of the vertically directional wirings 6 to connect between the cells 3 is facilitated. Nevertheless, when the places to make the straight lines 9 to cut vertically the cells 3 are made totally as the no cell arranged regions, because it causes insufficiency of the number of the cells, rough distribution of the straight lines 9 is investigated to find out the places A to be concentrated especially with the straight lines 9. Then the places A thereof are used as the no cell arranged regions 8 to improve arrangement of the cells 3. Accordingly, by providing the no cell arranged regions at the center part of the cells to be used as the vertically directionally wiring regions, the vertically directionally wiring regions at the center part of the chip are ensured, and the no wiring regions at automatically assembling time of the master slice LSI having the logically mounting ratio of less than 100% are reduced to the minimum.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to a master slice LSI in which a logic circuit is formed by circuit element arrays and cells provided on a chip, and in particular to a master slice LSI in which a logic circuit is configured by an array of circuit elements and cells provided on a chip. The present invention relates to a master slice LSI that takes this into consideration.

BACKGROUND ART A layout diagram of a conventional master slice LSI is shown in FIG. 1. In FIG. A desired logic circuit as L8I is constructed by arranging various cells in 5'lk rows on this circuit element row 2 and connecting them to each other, and each logic circuit includes transistors,
It is composed of one or a combination of circuit elements Y such as resistors and capacitors. Cell 3 is inter-cell wiring area 4
are connected using a horizontal wiring @5 running in the same direction as the circuit element row 2 and a vertical wiring @6 running in a direction orthogonal to the circuit element row 2.

Cell 3. Lateral alignment 4I5. An insulating layer is provided between the vertical wiring lines 6σ], and the horizontal wiring lines 5 and the vertical wiring lines 6 are connected by through holes 7.

Now, in an LSI as shown in FIG. 1, the wiring density between cells is high at the center of the LSI chip 1 and low at the periphery in order to shorten the wiring between each logic circuit. This increases the probability that the central part of the L8I chip 1 will be unwired during automatic assembly, and the unwired portion may be manually routed, and the mounting rate (percentage of the cell placement area on the circuit element row 2)
This is dealt with by lowering Y.

OBJECTS OF THE INVENTION An object of the present invention is to provide a master slice L8 IY that can reduce the number of automated unwired wires in the center of the chip.

In the present invention, an area where G cells are not placed on the circuit element row in the center of the chip is provided, and a wiring SV is provided in the ridge area where no cells are placed to connect the cells perpendicularly to the circuit element row. This makes it easy to automate wiring.

Embodiment of the Invention FIG. 2 shows a master slice LSI according to this embodiment, in which a plurality (5 columns) of circuit element rows 2 are formed in advance on an LSI chip 1, as in the conventional example. A logic circuit is constructed by bonding five cells on this circuit element row 2, and a desired logic circuit can be obtained by changing the cells 5 to be bonded.

These inter-cell-column wiring regions 4 are areas to which the lateral arrangement 5 is applied, as in the conventional example.

However, this master slice LSI differs from the conventional example, and the LS
A plurality of non-cell areas 8 are scattered in the center of the I-chip. In other words, there are two non-cell areas 8 in the middle part of the second and fourth columns above the top and bottom circuit element rows 2 in FIG. 2, and three non-cell areas 8 in the middle part of the third column. is provided.

The unwired area 8 is a vertical wiring 6 perpendicular to the circuit element row.
It can be used as a wiring area.

Therefore, LSIs with a high channel requirement rate especially in the vertical orientation A6
be beneficial to

In addition, in general, the vertical wiring 6 can be routed by passing over the cell 6, but this is only possible when constraints such as process conditions are satisfied (such as when the installed cell is a single layer). Since the vertical wiring @6 may be concentrated in the cell area 8 or the horizontal wiring 5 due to detour wiring may increase.
It is effective to use the area as a vertical wiring area.

Next, Figure 5.4? An effective positioning procedure for an area where no cells are placed will be explained using the following.

As shown in FIG. 3, desired cells 3 are placed on the chip 1, and the connection relationships between these cells 6 are indicated by lines 4I9 connecting the cells 3. By setting the area where these straight lines 419 cross five cells as a non-cell area, it becomes easy to install the vertical wiring 6 that connects the cells 3. but,
If the area where Direct@9 traverses Cell 5χ is set as a cell-unplaced area, the number of cells will be insufficient, so Direct41
Examine the approximate distribution of 9 and find the location A'1 where straight@9 is particularly concentrated.
¥: Find out.

These areas A7 are designated as non-cell area 8, and the placement of cells 3 is improved. FIG. 4 shows a schematic diagram of an LSI chip in which a cell-free area 8 is provided between cells.

In this way, since the area where no cells are placed is provided in the center of the chip and used as a vertical wiring area, the vertical wiring area in the center of the chip is secured, which is useful when automatically assembling a master slice LSI with a logic implementation rate of less than 100%. As a result, the chip size can be reduced, and the layout design man-hours and period can be shortened.

Although it depends on the chip size, it is also effective to limit the area to a specific area within one chip area and set the cell-unplaced area 8.

As described in detail, the master slice LSI according to the present invention provides an area where no cells are placed on the circuit element row at the center of the chip, and uses this area as a vertical wiring area. This has the effect of reducing the number of wiring lines.

[Brief explanation of the drawing]

FIG. 1 is a layout diagram of a conventional master slice LSI, FIG. 2 is a layout diagram of a master slice LSI according to the present invention, FIG. 5 is a cell connection relationship diagram for providing an area where no cells are placed, and FIG. is an LSI with a non-cell area
FIG. 2 is a schematic diagram of a chip. DESCRIPTION OF SYMBOLS 1...LSI chip, 2...Circuit element row, 3...Cell, 5...Horizontal wiring, 6...Vertical wiring, 8...Cell unplaced area, 9... Straight line. i/ Figure/1-2 Figure 1 3 Figure 1'-4-Figure

Claims (1)

[Claims] In a master slice LSI in which a large number of circuit elements are formed in multiple rows within an LSI chip, and a logic circuit Y is constructed by arranging cells serving as basic logic elements on these circuit elements and interconnecting them, a logic circuit Y is constructed. 1. A master slice LSI characterized in that a region where no cells are placed is provided on a circuit element column, and an area for interconnecting cells on different circuit element columns is provided on the circuit element column where no cells are placed.