JP2569477B2 - Gate array - Google Patents
Gate arrayInfo
- Publication number
- JP2569477B2 JP2569477B2 JP61021392A JP2139286A JP2569477B2 JP 2569477 B2 JP2569477 B2 JP 2569477B2 JP 61021392 A JP61021392 A JP 61021392A JP 2139286 A JP2139286 A JP 2139286A JP 2569477 B2 JP2569477 B2 JP 2569477B2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- cell
- wiring
- basic
- logic
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000149 penetrating effect Effects 0.000 claims description 5
- 239000004065 semiconductor Substances 0.000 claims description 2
- 230000002093 peripheral effect Effects 0.000 description 7
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体集積回路のゲートアレイの構造に関
する。Description: TECHNICAL FIELD The present invention relates to a gate array structure of a semiconductor integrated circuit.
本発明は、ゲートアレイにおいて、アレイ状に並んで
いるベーシックセルのセル列を、論理セルの配置に使用
するだけでなく、貫通電源としても使用できる構造に
し、チップ中心部への電源供給を容易にしたことにあ
る。According to the present invention, in a gate array, a structure in which a cell row of basic cells arranged in an array is used not only for arranging logic cells but also as a through power supply is provided, thereby facilitating power supply to a chip central portion. It is to have done.
従来のゲートアレイでは、アレイ上に論理セルのみを
配置していた。In a conventional gate array, only logic cells are arranged on the array.
〔発明が解決しようとする問題〕 しかし、ゲートアレイの場合には、外周部分に電源の
供給源があり、かつ、チップ中心部へは、供給量の少な
いラインしか配線できず、中心部に近いほど電源供給の
条件が悪くなり、ノイズによる悪影響が大きくなる問題
を有していた。[Problems to be Solved by the Invention] However, in the case of a gate array, there is a power supply source in the outer peripheral portion, and only a line with a small supply amount can be wired to the central portion of the chip, and it is close to the central portion. As the power supply condition becomes worse, the adverse effect of noise increases.
そこで、本発明はチップ中心部への電源供給を容易に
し、供給量を増加することにより回路の安定性，信頼性
を向上させることを目的としている。Accordingly, it is an object of the present invention to facilitate supply of power to a central portion of a chip, and to improve the stability and reliability of a circuit by increasing the supply amount.
上記問題を解決するために、本発明のゲートアレイ
は、アレイ状に並んでいるベーシックセル列の複数本の
セル列に対し貫通電源セルを配置できる様にした。配置
はマスク前の自動配置配線工程にてソフト的に自動処理
される為余計な工数は必要としない。In order to solve the above problem, the gate array according to the present invention is configured such that the through power supply cells can be arranged in a plurality of basic cell rows arranged in an array. No extra man-hours are required because the placement is automatically processed in software in the automatic placement and routing process before the mask.
そして、この貫通電源セルはベーシックセル上に電源
供給専用配線を形成してなるセルである。即ち、貫通電
源セルは、ベーシックセル上に論理回路構成用配線を形
成する代わりに別の配線を形成したものであり、該「別
の配線」は、例えば、第１図のベーシックセル13を示す
四辺形abcd内の四辺形abfe、hgcdの如く、ベーシックセ
ルの高さと幅に応じた寸法、形状を有する。このような
セルを構成することで単なる配線専用セルを形成するこ
とができる。そして、この「配線」を電源供給専用に用
いればこの配線は電源供給専用配線となり、この配線専
用セルは電源配線専用セルとなる。さらに、この電源配
線専用セルを第１図の符号16に示すようにベシックセル
が配置されるセル別のベーシックセル位置に複数隣接配
置すれば、該電源供給専用配線が左右に連結接続され、
これにより「貫通した」電源配線が形成されることにな
り、該「貫通した電源配線」は貫通電源ラインとなる。
そしてこの電源配線が貫通してなる態様にちなんで電源
配線専用セルを貫通電源セルと呼ぶ。そして、貫通電源
ラインを外周電源ラインと接続すれば本発明のゲートア
レイが得られる。The through power supply cell is a cell formed by forming a power supply exclusive wiring on a basic cell. That is, the through power supply cell is obtained by forming another wiring instead of forming the wiring for configuring the logic circuit on the basic cell, and the "different wiring" indicates, for example, the basic cell 13 in FIG. Like the quadrilaterals abfe and hgcd in the quadrilateral abcd, they have dimensions and shapes according to the height and width of the basic cell. By configuring such a cell, it is possible to form a simple wiring-only cell. If this "wiring" is used exclusively for power supply, this wiring becomes a power supply exclusive wiring, and this wiring exclusive cell becomes a power supply wiring exclusive cell. Further, if a plurality of the power supply dedicated cells are arranged adjacent to each other at the basic cell position for each cell where the basic cell is disposed as shown by reference numeral 16 in FIG.
As a result, a “penetrated” power supply wiring is formed, and the “penetrated power supply wiring” becomes a through power supply line.
Then, the cell dedicated to the power supply wiring is referred to as a penetrating power supply cell after the power supply wiring penetrates. Then, if the through power supply line is connected to the outer peripheral power supply line, the gate array of the present invention can be obtained.
すなわち、本発明のゲートアレイは、 複数のベーシックセルからなる複数のセル別と、該ベ
ーシックセルに電源電圧を供給する第１の電源配線とを
具備し、該ベーシックセル上に論理回路構成用配線を形
成して該配線に基づく所望の論理をなす論理セルを構成
してなるゲートアレイにおいて、 前記ベーシックセル上に論理回路構成用配線を形成す
るに代わりに電源供給専用配線を形成して貫通電源セル
を構成し、 該貫通電源セルが前記複数のセル列のなかの少なくと
も一つのセル別のベーシックセル位置に隣接配置され、 該隣接配置された前記貫通電源セルの前記電源供給専
用配線が前記少なくとも一つのセル列を貫通する第２の
電源配線を形成し、 該第２の電源配線は前記第１の電源配線に接続されて
成ることを特徴とする。That is, the gate array according to the present invention includes a plurality of cells each consisting of a plurality of basic cells, and a first power supply wiring for supplying a power supply voltage to the basic cells, and a logic circuit configuration wiring is provided on the basic cells. Forming a logic cell that forms a desired logic based on the wiring by forming a wiring dedicated to power supply instead of forming a wiring for configuring a logic circuit on the basic cell; A cell, wherein the through power supply cell is disposed adjacent to a basic cell position of at least one cell in the plurality of cell columns, and the power supply exclusive wiring of the adjacently disposed through power supply cell is at least one of A second power supply line penetrating one cell column is formed, and the second power supply line is connected to the first power supply line.
以下に本発明の実施例を図面にもとづいて説明する。 Hereinafter, embodiments of the present invention will be described with reference to the drawings.
第１図は、本発明のゲートアレイを実施した大規模集
積回路チップの一部を示したものである。アレイ状に並
んでいるベーシックセル列11の一部のセル列16を貫通電
源ライン14,15として使用している。14と15は互いに異
なる電位（VDDとVSS）の電源を供給し、かつ大電流容量
を供給できるような構造になっている。FIG. 1 shows a part of a large-scale integrated circuit chip on which a gate array according to the present invention is implemented. Some cell rows 16 of the basic cell row 11 arranged in an array are used as through power supply lines 14 and 15. 14 and 15 are configured to supply power of different potentials (V DD and V SS ) and to supply a large current capacity.
第２図は、セル列を複数本貫通電源ライン24,25とし
て使用した場合を示している。貫通電源ラインを複数本
設ける事により、さらに電源供給を増加させる事ができ
る。この貫通電源ラインは他のベーシックセル列に供給
されている電源ラインと同じく１層目金属配線を用いて
いる為２層目金属配線が横切ることができるので信号ラ
インの配線には支障ない。FIG. 2 shows a case where a cell row is used as a plurality of through power supply lines 24, 25. By providing a plurality of through power supply lines, the power supply can be further increased. This through power supply line uses the first-layer metal wiring like the power supply lines supplied to the other basic cell rows, so that the second-layer metal wiring can cross, so that there is no problem in the wiring of the signal line.
なお、第１図において、ベーシックセル13又は19は、
上下の実線と左右の破線とで囲まれた四辺形abcdであ
る。また、第１図におけて、例えば、３個のベーシック
セルを使用してNAND論理をなす１個の論理セルを形成し
た四辺形lmnk部分が論理セル17に相当する。また、第１
図において、例えば符号13の四辺形abfeとhgcdとが貫通
電源セルの配線部分即ち電源供給専用配線に相当する。In FIG. 1, the basic cell 13 or 19 is
It is a quadrilateral abcd surrounded by upper and lower solid lines and left and right broken lines. In FIG. 1, for example, a quadrilateral lmnk portion in which one basic logic cell is formed using three basic cells to form NAND logic corresponds to the logical cell 17. Also, the first
In the figure, for example, the quadrilaterals abfe and hgcd denoted by reference numeral 13 correspond to the wiring portion of the through power supply cell, that is, the power supply dedicated wiring.
以上のように、ベーシックセル列の一部のセル列を、
貫通電源として使用することにより、チップ中心部に十
分な電流を供給することが可能になり、回路の誤動作を
防止する効果がある。As described above, some cell rows of the basic cell row are
By using the power supply as a through power supply, it becomes possible to supply a sufficient current to the central portion of the chip, which has the effect of preventing malfunction of the circuit.
また、本発明は、該貫通電源セルが前記複数のセル列
のなかの少なくとも一つのセル列のベーシックセル位置
に隣接配置され、該隣接配置された前記貫通電源セルの
前記電源供給専用配線が前記少なくとも一つのセル列を
貫通する第２の電源配線を形成してなるため、貫通電源
セルを通常の論理セルと同様にセルライブラリとして用
意しておけばきわめて簡単な配置配線システムを使用す
るだけでチップ中心部に十分な電源の供給を可能とする
配線をなすことができる。また、このセルがセル列を貫
通する第２の電源配線を形成するため、既定のセル列を
電源配線のために使用でき、既存のレイアウトの規則性
を乱さない、そのため、設計規則の検証も容易であり、
配線工程での特殊な処理を必要としない。さらに、本願
発明では、貫通電源セルは、ベーシックセル上に論理回
路構成用配線を形成する代わりに電源供給専用配線を形
成するセルであるため、該貫通電源セルは電源配線のた
めにのみ使用される専用セルとして使用することができ
該セル内に論理回路を構成するための配線を形成する必
要はなく、そのための配線領域を確保する必要もない。
そのため、該貫通電源セルの大きさが許す範囲で太い電
源用配線をなすことができる。Further, in the present invention, the through power supply cell is disposed adjacent to a basic cell position of at least one of the plurality of cell columns, and the power supply dedicated wiring of the through power supply cell disposed adjacent to the plurality of cell columns is the power supply dedicated wiring. Since a second power supply wiring penetrating at least one cell row is formed, if a through power supply cell is prepared as a cell library like a normal logic cell, an extremely simple arrangement and wiring system can be used. Wiring that can supply a sufficient power can be formed at the center of the chip. In addition, since this cell forms a second power supply line penetrating the cell line, a predetermined cell line can be used for the power supply line and does not disturb the regularity of the existing layout. Easy,
No special processing is required in the wiring process. Further, in the present invention, the through power supply cell is a cell in which a power supply dedicated wiring is formed instead of forming a logic circuit configuration wiring on a basic cell. Therefore, the through power supply cell is used only for the power supply wiring. It is not necessary to form a wiring for forming a logic circuit in the cell, and it is not necessary to secure a wiring area therefor.
For this reason, a thick power supply wiring can be formed as far as the size of the through power supply cell allows.
第１図は、本発明のゲートアレイを実施した場合の部分
的な拡大図である。 11:ベーシックセル列（論理セルに使用したベーシック
セル列） 12:外周電源ライン 13:ベーシックセル 14,15:貫通電源ライン 16:貫通電源に使用したベーシックセル列 17,18:論理セル配置の一例 19:ベーシックセル 第２図は、本発明のゲートアレイを複数本実施した場合
の部分的な拡大図である。 21:ベーシックセル列（論理セルに使用したベーシック
セル列） 22:外周電源ライン 23:ベーシックセル列 24,25:貫通電源ライン 26:貫通電源に使用したベーシックセル列 27,28:論理セル配置の一例 第３図は、本発明のゲートアレイを実施した場合のチッ
プ全体の概略図である。 31:ベーシックセル列 32:外周電源ライン 33,34:貫通電源ライン 第４図は、従来ゲートアレイである論理セルのみを配置
した場合の部分的な拡大図である。 41:ベーシックセル列（論理セルに使用したベーシック
セル列） 42:外周電源ライン 43:ベーシックセル 44,45:論理セル配置の一例 第５図は、従来ゲートアレイのチップ全体の概略図であ
る。 51:ベーシックセル列 52:外周電源ラインFIG. 1 is a partially enlarged view when the gate array of the present invention is implemented. 11: Basic cell row (basic cell row used for logic cell) 12: Peripheral power supply line 13: Basic cell 14, 15: Through power supply line 16: Basic cell row used for through power supply 17, 18: Example of logic cell layout 19: Basic Cell FIG. 2 is a partially enlarged view when a plurality of gate arrays of the present invention are implemented. 21: Basic cell row (basic cell row used for logic cell) 22: Peripheral power supply line 23: Basic cell row 24, 25: Through power supply line 26: Basic cell row used for through power supply 27, 28: Logical cell layout Example FIG. 3 is a schematic view of the entire chip when the gate array of the present invention is implemented. 31: Basic cell row 32: Peripheral power supply line 33, 34: Through power supply line FIG. 4 is a partially enlarged view when only a logic cell which is a conventional gate array is arranged. 41: Basic cell array (Basic cell array used for logic cells) 42: Peripheral power supply line 43: Basic cells 44, 45: Example of logic cell arrangement FIG. 5 is a schematic diagram of the entire chip of a conventional gate array. 51: Basic cell row 52: Peripheral power line
Claims (1)
列と、該ベーシックセルに電源電圧を供給する第１の電
源配線とを具備し、該ベーシックセル上に論理回路構成
用配線を形成して該配線に基づく所望の論理をなす論理
セルを構成してなるゲートアレイにおいて、 前記ベーシックセル上に論理回路構成用配線を形成する
に代わりに電源供給専用配線を形成して貫通電源セルを
構成し、 該貫通電源セルが前記複数のセル列のなかの少なくとも
一つのセル別のベーシックセル位置に隣接配置され、 該隣接配置された前記貫通電源セルの前記電源供給専用
配線が前記少なくとも一つのセル列を貫通する第２の電
源配線を形成し、 該第２の電源配線は前記第１の電源配線に接続されて成
ることを特徴とするゲートアレイ。1. A semiconductor device comprising: a plurality of cell columns including a plurality of basic cells; and a first power supply wiring for supplying a power supply voltage to the basic cells, wherein a wiring for forming a logic circuit is formed on the basic cells. In a gate array configured to form a logic cell that performs a desired logic based on the wiring, a through power supply cell is formed by forming a power supply dedicated wiring instead of forming a logic circuit configuration wiring on the basic cell. Wherein the through power supply cell is disposed adjacent to a basic cell position of at least one of the plurality of cell rows, and the power supply dedicated wiring of the adjacently disposed through power supply cell is provided in the at least one cell row. A second power supply wiring penetrating through the first power supply wiring, the second power supply wiring being connected to the first power supply wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61021392A JP2569477B2 (en) | 1986-02-03 | 1986-02-03 | Gate array |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61021392A JP2569477B2 (en) | 1986-02-03 | 1986-02-03 | Gate array |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62179743A JPS62179743A (en) | 1987-08-06 |
| JP2569477B2 true JP2569477B2 (en) | 1997-01-08 |
Family
ID=12053790
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61021392A Expired - Lifetime JP2569477B2 (en) | 1986-02-03 | 1986-02-03 | Gate array |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2569477B2 (en) |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60173855A (en) * | 1984-02-20 | 1985-09-07 | Hitachi Ltd | Integrated circuit |
| JPH0630377B2 (en) * | 1984-06-15 | 1994-04-20 | 株式会社日立製作所 | Semiconductor integrated circuit device |
-
1986
- 1986-02-03 JP JP61021392A patent/JP2569477B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62179743A (en) | 1987-08-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |