JP2776513B2 - Semiconductor integrated circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit in which a wiring channel of a gate array is improved.

[Conventional technology]

Generally, in a gate array type semiconductor integrated circuit, a plurality of logic blocks are arranged on a semiconductor integrated circuit chip,
A channel for wiring is formed between these logic blocks, and a power supply bus is extended here. The power supply to the logical blocks is performed by arbitrarily connecting the power bus to each logical block, and the required circuit is connected by connecting each logical block with a signal line using a wiring channel. Is composed.

By the way, the performance of this type of semiconductor integrated circuit is defined by the delay time between gates connected with a fixed wiring length.
The breakdown of the delay time consists of the delay of the gate alone and the wiring delay. The former is determined by the adopted process technology, and the latter is determined by the intersection of the wiring layers in addition to the process technology.

[Problems to be Solved by the Invention] In the above-mentioned conventional semiconductor integrated circuit, the power supply bus is usually provided in a different layer from the signal line, and the line width is several to several tens times as large as the signal line for stable power supply. Is formed.
Therefore, the probability that the signal line crosses the power supply bus in the wiring channel or the like is large, thereby increasing the interlayer capacitance of the signal line and affecting the wiring delay. In particular, since the signal line connecting between the logic blocks is provided relatively long in the wiring channel, the interlayer capacitance greatly affects the wiring delay, which causes the performance of the semiconductor integrated circuit described above to deteriorate. .

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor integrated circuit in which a power supply bus and a signal line in a wiring channel are prevented from intersecting to improve a wiring delay.

[Means for solving the problem]

In the semiconductor integrated circuit of the present invention, a power supply bus is extended so as to surround a plurality of logic blocks arranged in a grid pattern, and the tip is opened from the power supply bus toward each logic block. A branch line is extended, and each logical block is electrically connected to the branch line by a wiring formed in each logical block, and the branch line does not exist in a wiring channel defined between the logical blocks. In this wiring channel, only signal lines for interconnecting the respective logical blocks are provided.

[Action]

With the above-described configuration, it is possible to prevent a signal line for connecting logical blocks extending relatively long from intersecting with the power supply bus, thereby preventing an increase in the wiring capacity of this signal line.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a plan view schematically showing a semiconductor integrated circuit chip according to one embodiment of the present invention, and 1 indicates a semiconductor integrated circuit chip. The semiconductor integrated circuit chip 1 has a plurality of (here, four) logic blocks 2A, 2B, 2C, and 2D in which a plurality of logic gates constituting a logic circuit are arranged in a grid pattern. A wiring channel 3 is formed between the logical blocks 2A, 2B, 2C, and 2D. A power supply bus 4 for supplying power to each logical block is provided around the logical blocks 2A, 2B, 2C, 2D, and a branch line is extended to each logical block. However, the power supply bus 4 has its wiring pattern formed so as not to exist in the wiring channel 3.

Each of the logic blocks 2A, 2B, 2C, and 2D has a wiring formed in each block, interconnects logic gates in the same block, and differs according to a signal line 5 extending through the wiring channel 3. The logic gates of the logic block are interconnected to form a required circuit. Each logical block is connected to the power supply bus 4 by a wiring formed in each block.

According to this configuration, since the power supply bus 4 does not extend to the wiring channel 3, the signal line 5 connecting the logical blocks does not cross the power supply bus 4 in the wiring channel 3. . For this reason, in the wiring channel 3, there is no wiring capacitance between the power supply bus 4 and the signal line 5, whereby an increase in the capacity of the relatively long inter-block signal line 5 can be prevented, and the wiring delay To prevent performance degradation due to an increase in

The signal line 5 may intersect the power supply bus 4 in each of the logic blocks 2A, 2B, 2C, and 2D. However, the wiring delay is a problem when the pure wiring length between logic gates is extremely long. Therefore, the influence of the wiring capacity due to the power supply bus is extremely small in a short wiring inside the logical block, and the performance is hardly deteriorated.

Needless to say, the present invention can be similarly applied to a semiconductor integrated circuit having four or more logic blocks. Further, the present invention can be similarly applied to a case where the arrangement of each logical block is different from that of the embodiment.

〔The invention's effect〕

As described above, according to the present invention, since a wiring channel to which a power bus is not provided is provided between a plurality of logical blocks, a signal line connecting each logical block is provided to be extended to this wiring channel. Accordingly, it is possible to prevent the signal line extending relatively long from intersecting with the power supply bus, to prevent an increase in the wiring capacity of the signal line, to reduce a wiring delay, and to prevent performance degradation.

[Brief description of the drawings]

FIG. 1 is a schematic plan view of a chip according to one embodiment of the present invention. 1 ... Semiconductor integrated circuit chip, 2A, 2B, 2C, 2D ... Logic block, 3 ... Wiring channel, 4 ... Power bus, 5 ...
…Signal line.

Claims (1)

(57) [Claims] In a semiconductor integrated circuit in which a plurality of logic blocks are arranged in a grid pattern, a power bus is extended so as to surround the plurality of logic blocks, and each of the logic blocks is separated from the power bus. Each logical block is electrically connected to the branch line by a wiring formed in each logical block, and the branch line is defined between the logical blocks. A semiconductor integrated circuit, wherein only a signal line for interconnecting the logical blocks is provided in the wiring channel.